Invention Grant
US06790756B2 Self aligned channel implant, elevated S/D process by gate electrode damascene
有权
自对准通道植入,栅电极镶嵌提高S / D工艺
- Patent Title: Self aligned channel implant, elevated S/D process by gate electrode damascene
- Patent Title (中): 自对准通道植入,栅电极镶嵌提高S / D工艺
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Application No.: US10385954Application Date: 2003-03-11
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Publication No.: US06790756B2Publication Date: 2004-09-14
- Inventor: Chu-Wei Hu , Jiue-Wen Weng , Chung-Te Lin , So Wein Kuo
- Applicant: Chu-Wei Hu , Jiue-Wen Weng , Chung-Te Lin , So Wein Kuo
- Main IPC: H01L213205
- IPC: H01L213205

Abstract:
A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.
Public/Granted literature
- US20030170957A1 Novel self aligned channel implant, elevated S/D process by gate electrode damascene Public/Granted day:2003-09-11
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