摘要:
In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region.
摘要:
A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.
摘要:
A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.
摘要:
A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate. The SiON anti-reflective coating layer is removed wherein the protective oxide layer protects the polysilicon lines and the silicon substrate from damage to complete fabrication of polysilicon lines in the manufacture of an integrated circuit device.
摘要:
Defining an oxide define region (ODR) without using a photomask is disclosed. Pad oxide and a stop layer are deposited over peaks of a substrate of a semiconductor wafer. The pad oxide may be silicon oxide, whereas the stop layer may be silicon nitride. Oxide, such as high-density plasma (HDP) oxide, is deposited over the pad oxide, the stop layer, and valleys of the substrate of the semiconductor wafer. A hard mask, such as silicon nitride, is deposited over the oxide, and photoresist is deposited over the hard mask. The photoresist is etched back until peaks of the hard mask are exposed. The peaks of the hard mask and the oxide underneath are etched through to the stop layer, and the photoresist is removed. Chemical-mechanical planarization (CMP) can then be performed on the hard mask that remains and the oxide underneath through to the stop layer, and the stop layer removed.
摘要:
A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers. By forming the gate spacers and the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and spacers where the gate poly protrudes above the spacers thus enhancing the formation of silicide.
摘要:
A process for forming a dual damascene opening, in a composite insulator layer, comprised of an overlying, wide diameter opening, used to accommodate a metal interconnect structure, and comprised of an underlying, narrow diameter opening, used to accommodate a metal via structure, has been developed. The process features the use of conventional photolithographic and anisotropic dry etching procedures, used to create an initial dual damascene opening, in the composite insulator layer. The subsequent formation of insulator spacers, on the vertical sides of the initial dual damascene opening, however, results in a final dual damascene opening, featuring a diameter smaller than the diameter displayed with the initial dual damascene opening.
摘要:
A method of forming a FET with an having a self-aligned pocket implant, comprising the following steps. A substrate is formed having a substrate dielectric layer thereon and a first oxide layer over the substrate dielectric layer. The first oxide layer having an upper surface. A trench is formed through the oxide layer, the substrate dielectric layer, and partially through the substrate. The trench having a bottom and side walls. A second oxide layer is formed along the bottom and said side walls of said trench within the substrate. A dopant is selectively ion implanted into the substrate is achieved to form lightly doped layers adjacent the side walls of the trench within the substrate. A self-aligned channel implant and a pocket implant are ion implanted at predetermined respective depths in the substrate below the trench bottom is achieved. Side-wall spacers on the side walls of the trench are then formed with the side-wall spacers each having a top surface below the upper surface of the first oxide layer. A gate dielectric layer is formed on the bottom of the trench between the side-wall spacers. A planarized gate electrode is formed that has an upper surface substantially coextensive with the upper surface of the first oxide layer. The first oxide layer and the substrate dielectric layer are removed. A dopant is ion implanted into the substrate to form heavily doped layers adjacent the side wall spacers.
摘要:
In accordance with one embodiment, the present invention provides a bipolar junction transistor including an emitter region; a base region; a first isolation between the emitter region and the base region; a gate on the first isolation region and overlapping at least a portion of a periphery of the emitter region; a collector region; and a second isolation between the base region and the collector region.
摘要:
A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate. Using the remaining non-conformal oxide as a mask, we implant impurities of the second conductivity type through the second openings to form second wells. The remaining non-conformal oxide layer and the screen oxide layer are removed.