发明授权
US06816979B1 Configurable fast clock detection logic with programmable resolution
有权
可配置的快速时钟检测逻辑，可编程分辨率
- 专利标题： Configurable fast clock detection logic with programmable resolution
- 专利标题（中）： 可配置的快速时钟检测逻辑，可编程分辨率
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申请号： US09775372申请日： 2001-02-01
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公开(公告)号： US06816979B1公开(公告)日： 2004-11-09
- 发明人: Jiann-Cheng Chen , Somnath Paul , S. Babar Raza
- 申请人： Jiann-Cheng Chen , Somnath Paul , S. Babar Raza
- 主分类号： G06F112
- IPC分类号： G06F112
摘要：
An apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and present a faster clock signal of the synchronized clock signals.
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