专利检索 ap:("Jiann-Cheng Chen" OR "Somnath Paul" OR "S. Babar Raza") AND inv:"Jiann-Cheng Chen" 第 1 页

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发明授权
Configurable fast clock detection logic with programmable resolution 有权
标题翻译：可配置的快速时钟检测逻辑，可编程分辨率

公开(公告)号：US06816979B1

公开(公告)日：2004-11-09

申请号：US09775372

申请日：2001-02-01

申请人： Jiann-Cheng Chen , Somnath Paul , S. Babar Raza

发明人： Jiann-Cheng Chen , Somnath Paul , S. Babar Raza

IPC分类号： G06F112

CPC分类号： G06F1/12

摘要： An apparatus comprising a first logic circuit and a second logic circuit. The first logic circuit may comprise one or more counters and may be configured to synchronize a plurality of input clock signals. The second logic circuit may be configured to detect and present a faster clock signal of the synchronized clock signals.