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    Multiple byte data path encoding/decoding device and method
    3.
    发明授权
    Multiple byte data path encoding/decoding device and method 有权
    多字节数据路径编码/解码装置及方法

    公开(公告)号：US07138930B1

    公开(公告)日：2006-11-21

    申请号：US10937138

    申请日：2004-09-09

    申请人： Somnath Paul ,  Hamid Khodabandehlou

    发明人： Somnath Paul ,  Hamid Khodabandehlou

    IPC分类号： H03M7/00

    CPC分类号： H03M5/145 ,  H04L25/14 ,  H04L25/4906

    摘要： Systems and methods for performing encoding and/or decoding can include an input data path that receives multiple input data values having an order (significance) with respect to one another. Each input data value can be applied to multiple compute paths (106-1 to 106-N), each of which can precompute multiple output values based on a different predetermined disparity value. Multiplexers (114-1 to 114-N) can output one precomputed output value according to a disparity value corresponding to a previous input data value in the order.

    摘要翻译： 用于执行编码和/或解码的系统和方法可以包括输入数据路径，其接收具有相对于彼此的顺序（重要性）的多个输入数据值。 每个输入数据值可以应用于多个计算路径（106-1至106-N），每个计算路径可以基于不同的预定差异值预先计算多个输出值。 多路复用器（114-1至114-N）可以根据与先前输入数据值相对应的视差值输出一个预计算的输出值。

    Method of maximizing bandwidth efficiency in a protocol processor
    7.
    发明授权
    Method of maximizing bandwidth efficiency in a protocol processor 失效
    最大化协议处理器带宽效率的方法

    公开(公告)号：US07496109B1

    公开(公告)日：2009-02-24

    申请号：US10777286

    申请日：2004-02-11

    申请人： Jay K. Gupta ,  Somnath Paul

    发明人： Jay K. Gupta ,  Somnath Paul

    IPC分类号： H04L12/56

    CPC分类号： H04L47/22 ,  H04L49/90

    摘要： A packet processing system including an encapsulator engine, and a packet pre-processor coupled to the encapsulator engine. The packet pre-processor calculates a variation between an input data rate and a pre-determined output data rate. The input data rate is based on a number of data read requests. The packet pre-processor compensates for the variation by modifying the number of data read requests.

    摘要翻译： 一种分组处理系统，包括封装引擎和耦合到封装引擎的分组预处理器。 分组预处理器计算输入数据速率和预定输出数据速率之间的变化。 输入数据速率基于多个数据读取请求。 分组预处理器通过修改数据读取请求的数量来补偿变化。

    Scheduling store-forwarding of back-to-back multi-channel packet fragments
    8.
    发明授权
    Scheduling store-forwarding of back-to-back multi-channel packet fragments 有权
    调度背对背多通道数据包片段的存储转发

    公开(公告)号：US07379467B1

    公开(公告)日：2008-05-27

    申请号：US10841774

    申请日：2004-05-06

    申请人： Somnath Paul ,  Sanjay Rekhi

    发明人： Somnath Paul ,  Sanjay Rekhi

    IPC分类号： H04L12/28 ,  H04L12/56 ,  H04J3/16

    CPC分类号： H04L49/9094 ,  H04L12/5601 ,  H04L49/608 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/5652 ,  H04L2012/5679

    摘要： Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The scheduler may be configured to operate according to a scheduling policy. The scheduling policy may include a set of priorities to determine an order of scheduling writes to the output memory from a plurality of data assemblers. The scheduling policy may also include selecting one or more of the plurality of data assemblers having a fill level greater than twice an input data path width of an input data bus and having no end-of-packet (EOP) or start-of-packet (SOP) as a first priority, selecting one or more of the plurality of data assemblers having a fill level greater than twice the input data path width of the input data bus, and not covered in the first priority selection, as a second priority, selecting one or more of the plurality of data assemblers having a fill level greater than the input data path width of the input data bus, and not covered in the first and second priority selections, as a third priority, and selecting one or more of the plurality of data assemblers having an end-of-packet (EOP) as a fourth priority.

    摘要翻译： 公开了一种用于调度背对背多信道分组片段的存储转发的接口的装置和方法。 该装置可以包括数据提取块，多个数据组装器，调度器和输出存储器。 调度器可以被配置为根据调度策略进行操作。 调度策略可以包括一组优先级，以确定从多个数据汇编器调度对输出存储器的写入的顺序。 调度策略还可以包括选择多个数据汇编器中的一个或多个具有大于输入数据总线的输入数据路径宽度的两倍的填充水平并且没有分组结束（EOP）或分组开始 （SOP）作为第一优先级，选择所述多个数据组合器中的一个或多个具有大于输入数据总线的输入数据路径宽度的两倍的填充水平，并且在第一优先级选择中不被覆盖，作为第二优先级， 选择所述多个数据组合器中的一个或多个具有大于所述输入数据总线的输入数据路径宽度的填充水平，并且在第一和第二优先级选择中未被覆盖的第一优先级和第二优先级，并且选择一个或多个 具有作为第四优先级的分组结束（EOP）的多个数据组装器。

    First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access
    9.
    发明授权
    First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access 有权
    先进先出（FIFO）存储器，用于通过使用由单位访问增加的读取和写入指针以及单位访问的一部分来缓冲分组片段

    公开(公告)号：US07272675B1

    公开(公告)日：2007-09-18

    申请号：US10841865

    申请日：2004-05-06

    申请人： Somnath Paul ,  Sanjay Rekhi

    发明人： Somnath Paul ,  Sanjay Rekhi

    IPC分类号： G06F3/00 ,  G06F5/00 ,  G06F9/40

    CPC分类号： G06F5/10 ,  G06F5/14 ,  G06F2205/061 ,  G06F2205/106 ,  G06F2205/108

    摘要： Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least one of a unit access per read and a fraction of the unit access per read, and a write pointer of the FIFO memory, the write pointer to increment by at least one of a unit access per write and a fraction of the unit access per write.

    摘要翻译： 公开了一种在用于调度背对背多信道分组片段的存储转发的接口中使用的装置和方法，包括先进先出（FIFO）存储器，FIFO存储器的读指针， 所述读取指针通过每次读取的单位访问和每次读取的单位访问的一小部分以及FIFO存储器的写入指针中的至少一个来增加，所述写入指针通过每次写入的单位访问中的至少一个来增加，以及 每次写入单位访问的一小部分。

    Method and apparatus for re-accessing a FIFO location
    10.
    发明授权
    Method and apparatus for re-accessing a FIFO location 失效
    重新访问FIFO位置的方法和装置

    公开(公告)号：US06957309B1

    公开(公告)日：2005-10-18

    申请号：US10324308

    申请日：2002-12-18

    申请人： Jay K. Gupta ,  Somnath Paul

    发明人： Jay K. Gupta ,  Somnath Paul

    IPC分类号： G06F5/10 ,  G06F12/02

    CPC分类号： G06F5/10 ,  G06F2205/062

    摘要： In one embodiment, the invention is an apparatus. The apparatus includes a FIFO array having a first plurality of memory elements, each memory element having a predetermined number of bits, the FIFO array having a read pointer. The apparatus also includes a FIFO control register array having a second plurality of memory elements, each memory element of the second plurality corresponding to a memory element of the first plurality of memory elements, the read pointer suitable for accessing the FIFO control register array. The apparatus further includes a control logic block coupled to the FIFO control register array and the FIFO array. The control logic block is to receive a data value of the memory element of the FIFO control register array pointed to by the read pointer. The control logic block is also to signal the read pointer to stall responsive to the data value having a first value.

    摘要翻译： 在一个实施例中，本发明是一种装置。 该装置包括具有第一多个存储元件的FIFO阵列，每个存储器元件具有预定数量的位，该FIFO阵列具有读指针。 该装置还包括具有第二多个存储元件的FIFO控制寄存器阵列，第二多个存储元件的每个存储元件对应于第一多个存储器元件的存储器元件，该读指针适于访问FIFO控制寄存器阵列。 该装置还包括耦合到FIFO控制寄存器阵列和FIFO阵列的控制逻辑块。 控制逻辑块用于接收由读指针指向的FIFO控制寄存器阵列的存储元件的数据值。 响应于具有第一值的数据值，控制逻辑块还将读取指针发信号通知停止。