Invention Grant
- Patent Title: Combinational equivalence checking methods and systems with internal don't cares
- Patent Title (中): 组合等价检查方法和内部系统不需要关心
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Application No.: US10230976Application Date: 2002-08-28
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Publication No.: US06842884B2Publication Date: 2005-01-11
- Inventor: Yung-Te Lai , Chioumin Chang , Kung-Chien Chen , Chih-Chang Lin
- Applicant: Yung-Te Lai , Chioumin Chang , Kung-Chien Chen , Chih-Chang Lin
- Applicant Address: US CA Milpitas
- Assignee: Verplex Systems, Inc.
- Current Assignee: Verplex Systems, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Heller Ehrman White & McAuliffe
- Agent Paul Davis
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An equivalence checking method provides first and second logic functions. Don't care gates are inserted for don't care conditions in the first and second logic functions. The insertion of the don't care gates creates a first intermediate circuit and a second intermediate circuit. All 3DC gates of the first intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. All 3DC gates of the second intermediate circuit are propagated and merged into a single 3DC gate when 3DC gates and SDC gates coexist in either of the first and second intermediate circuits. First and second circuits are produced in response to propagating and merging the 3DC gates. A combinational equivalence check is then performed of the first circuit to the second circuit under different equivalence relations.
Public/Granted literature
- US20040044975A1 Combinational equivalence checking methods and systems with internal don't cares Public/Granted day:2004-03-04
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