Invention Grant
- Patent Title: MOS transistor and fabrication method thereof
- Patent Title (中): MOS晶体管及其制造方法
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Application No.: US10300293Application Date: 2002-11-20
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Publication No.: US06853040B2Publication Date: 2005-02-08
- Inventor: Kyung-Oun Jang , Sun-Hak Lee
- Applicant: Kyung-Oun Jang , Sun-Hak Lee
- Applicant Address: KR Bucheon
- Assignee: Fairchild Korea Semiconductor Ltd.
- Current Assignee: Fairchild Korea Semiconductor Ltd.
- Current Assignee Address: KR Bucheon
- Agency: Alston & Bird LLP
- Priority: KR2000-2023 20000117
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092 ; H01L29/08 ; H01L29/10 ; H01L29/423 ; H01L29/78 ; H01L29/76

Abstract:
A CMOS transistor is provided having a relatively high breakdown voltage. The CMOS transistor includes an N-type epitaxial layer on a P-type substrate. Between the substrate and epitaxial layer are a heavily doped N-type buried layer and a heavily doped P-type base layer. An N-type sink region is proximate the edge of the NMOS region, and twin wells are in the area surrounded with the sink region. N+ source and drain regions are formed in respective wells. As the sink region is interposed between the drain and isolation regions, a breakdown occurs between the sink and isolation regions when a high voltage is applied. Twin wells are also formed in the PMOS region. P+ source and drain regions are formed in respective wells. As the N-type well surrounds the source and bulk regions, a breakdown occurs between a buried region and the isolation region when a high voltage is applied.
Public/Granted literature
- US20030071314A1 MOS transistor and fabrication method thereof Public/Granted day:2003-04-17
Information query
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