Invention Grant
- Patent Title: High density interconnection test connector especially for verification of integrated circuits
- Patent Title (中): 高密度互连测试连接器特别用于集成电路的验证
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Application No.: US09735684Application Date: 2000-12-13
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Publication No.: US06861855B2Publication Date: 2005-03-01
- Inventor: Jean-Michel Jurine , Isabelle George
- Applicant: Jean-Michel Jurine , Isabelle George
- Applicant Address: FR
- Assignee: Upsys Probe Technology SAS
- Current Assignee: Upsys Probe Technology SAS
- Current Assignee Address: FR
- Agency: Piper Rudnick LLP
- Priority: FR9915679 19991213
- Main IPC: G01R31/26
- IPC: G01R31/26 ; G01R1/067 ; G01R1/073 ; G01R3/00 ; H01L21/66 ; H01R13/02 ; G01R31/02

Abstract:
This invention pertains to a high density interconnection test connector intended especially for verification of integrated circuits, including a plate supporting a multiplicity of conductive pins one of the ends of which forms a contact zone with the electronic circuit to be tested and the other end forms a contact zone with a connecting plate that has a connection means with the test equipment, with the conductive pins presenting a form that is capable of ensuring flexibility and including a longitudinal component, characterized in that the pins present a succession of at least three arc-shaped sections (4, 5, 6) in alternating directions extended on both sides by rectilinear segments that are mobile according to one degree of freedom in axial translation, with the pins being inserted in the front plates.
Public/Granted literature
- US20010031575A1 High density interconnection test connector especially for verification of integrated circuits Public/Granted day:2001-10-18
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