发明授权
- 专利标题： Method for manufacturing semiconductor device
- 专利标题（中）： 制造半导体器件的方法
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申请号： US10673374申请日： 2003-09-30
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公开(公告)号： US06867079B2公开(公告)日： 2005-03-15
- 发明人: Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
- 申请人： Atsushi Kurokawa , Toshiaki Kitahara , Hiroshi Inagawa , Yoshinori Imamura
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Miles & Stockbridge P.C.
- 优先权： JP2002-038430 20020215
- 主分类号： H01L29/872
- IPC分类号： H01L29/872 ; H01L21/3205 ; H01L21/329 ; H01L21/331 ; H01L21/822 ; H01L21/8222 ; H01L23/52 ; H01L27/04 ; H01L27/06 ; H01L29/47 ; H01L29/737 ; H01L21/338
摘要：
The present invention achieves the enhancement of a manufacturing yield factor and the reduction of manufacturing cost in a manufacturing method of a semiconductor device having a hetero junction bipolar transistor (HBT), a Schottky diode and a resistance element. The present invention is directed to the manufacturing method of a semiconductor device in which respective semiconductor layers which become a sub collector layer, a collector layer, a base layer, a wide gap emitter layer and an emitter layer are sequentially formed over one surface of a semiconductor substrate and, thereafter, respective semiconductor layers are processed to form the hetero junction bipolar transistor, the Schottky diode and the resistance element in a monolithic manner. An emitter electrode of the hetero junction bipolar transistor, a Schottky electrode of the Schottky diode and a resistance film of the resistance element are simultaneously formed using a same material (for example, WSiN). Accordingly, the man-hours can be reduced and the manufacturing cost of the semiconductor device can be reduced.
公开/授权文献
- US20040063292A1 Method for manufacturing semiconductor device 公开/授权日：2004-04-01
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