发明授权
- 专利标题: Semiconductor device having a trench isolation and method of fabricating the same
- 专利标题(中): 具有沟槽隔离的半导体器件及其制造方法
-
申请号: US10237022申请日: 2002-09-09
-
公开(公告)号: US06875663B2公开(公告)日: 2005-04-05
- 发明人: Toshiaki Iwamatsu , Takashi Ipposhi , Takuji Matsumoto , Shigenobu Maeda
- 申请人: Toshiaki Iwamatsu , Takashi Ipposhi , Takuji Matsumoto , Shigenobu Maeda
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corp.
- 当前专利权人: Renesas Technology Corp.
- 当前专利权人地址: JP Tokyo
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
- 优先权: JP2001-387522 20011220
- 主分类号: H01L21/76
- IPC分类号: H01L21/76 ; H01L21/336 ; H01L21/762 ; H01L21/84 ; H01L27/08 ; H01L27/12 ; H01L29/786
摘要:
The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
公开/授权文献
信息查询
IPC分类: