A clock switching circuit has a clock output circuit and clock signal transfer circuits. The output circuit provides a selected clock signal. The transfer circuits receive input clock signals and select signals, and output transfer signals to the output circuit. Each of the transfer circuits includes a transmitting circuit, a generating circuit and a passing circuit. The transmitting circuit is connected to the output circuit, and receives the select signal and provides the received select signal responsive to the selected clock signal. The generating circuit is connected to the transmitting circuit, and provides an internal select signal responsive to the received select signal and the input clock signal. The passing circuit is connected to the generating circuit and the output circuit, and provides the input clock signal to the output circuit responsive to the internal select signal.