公开(公告)号：US07187605B2

公开(公告)日：2007-03-06

申请号：US10747400

申请日：2003-12-30

Applicant: Takeo Takahashi

Inventor： Takeo Takahashi

IPC: G11C7/00

CPC classification number: G11C7/12 ,  G11C17/12

Abstract: A mask ROM small in circuit scale and low in consumption power has an n-type select transistor having a drain connected to a corresponding one of bit lines, a source connected to a data line, and a gate having a corresponding one of select signals input thereto. A p-type precharge transistor has a drain connected to a corresponding one of bit lines, a source connected to a power line, and a gate having a corresponding one of the select signals input thereto. Because the bit line is precharged by using a precharge transistor opposite in conductivity type to the select transistors, it is satisfactory to provide one precharge transistor for one bit line, greatly reducing the circuit scale.

Abstract translation: 电路规模小，功耗低的掩模ROM具有n型选择晶体管，其具有连接到相应的一条位线的漏极，连接到数据线的源极和具有相应的一个选择信号输入的栅极 到此。 p型预充电晶体管具有连接到对应的一个位线的漏极，连接到电力线的源极和具有输入到其中的选择信号中的相应一个的栅极。 由于通过使用与选择晶体管相反的导电类型的预充电晶体管对位线进行预充电，所以为一位线提供一个预充电晶体管是令人满意的，这大大降低了电路规模。

公开(公告)号：US07176127B2

公开(公告)日：2007-02-13

申请号：US11083311

申请日：2005-03-18

Applicant: Makiko Nakamura

Inventor： Makiko Nakamura

IPC: H01L21/4763

CPC classification number: H01L23/5226 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An adhesion layer for causing a plug for electrically connecting a lower wiring and an upper wiring opposite to each other with an interlayer insulating film interposed therebetween to adhere to the interlayer insulating film is formed within a through hole for forming the plug, based on a predetermined aspect ratio represented by a ratio of a depth dimension of the through hole to a diameter dimension of the through hole.

Abstract translation: 在用于形成插塞的通孔内，基于预定的粘合层形成用于使用于使下布线和彼此相对的上布线的插塞之间插入层间绝缘膜以粘附到层间绝缘膜的粘合层， 纵横比由通孔的深度尺寸与通孔的直径尺寸的比率表示。

公开(公告)号：US07167050B2

公开(公告)日：2007-01-23

申请号：US10693500

申请日：2003-10-27

Applicant: Koji Suzuki

Inventor： Koji Suzuki

IPC: H03F3/45

CPC classification number: H03F3/3033 ,  H03F3/45183 ,  H03F2203/45564 ,  H03F2203/45592 ,  H03F2203/45674

Abstract: An operational amplifier including a differential input section generating a first signal as a differential voltage between two input signals; an amplifying section amplifying the first signal into second and third complementary signals; a first MOS transistor between a first supply voltage and an output node, a conduction state of the first MOS transistor controlled responsive to the second signal; a second MOS transistor between a second supply voltage and the output node, a conduction state of the second MOS transistor controlled responsive to the third signal; and a step-up section stepping up the first and second supply voltages to generate a step-up voltage higher than the first and second supply voltages, the amplifying section driven by the step-up voltage so that an absolute value of the maximum level of the second or third signal becomes larger than the absolute value of the first or second supply voltage.

Abstract translation: 运算放大器，包括差分输入部分，其产生作为两个输入信号之间的差分电压的第一信号; 放大部分，将第一信号放大为第二和第三互补信号; 在第一电源电压和输出节点之间的第一MOS晶体管，响应于第二信号控制的第一MOS晶体管的导通状态; 在第二电源电压和输出节点之间的第二MOS晶体管，响应于第三信号控制的第二MOS晶体管的导通状态; 以及升压部分升高第一和第二电源电压以产生高于第一和第二电源电压的升压电压，放大部分由升压电压驱动，使得最大电平的绝对值 第二或第三信号变得大于第一或第二电源电压的绝对值。

公开(公告)号：US07161660B2

公开(公告)日：2007-01-09

申请号：US11017783

申请日：2004-12-22

Applicant: Yo-Han Ahn ,  Seok-Ryeul Lee ,  Jung-Sung Hwang ,  Tae-Jin Hwang ,  Byung-Moo Lee

Inventor： Yo-Han Ahn ,  Seok-Ryeul Lee ,  Jung-Sung Hwang ,  Tae-Jin Hwang ,  Byung-Moo Lee

IPC: G03B27/72

CPC classification number: G03F7/70558

Abstract: A management system and method of a reticle in an exposing process are disclosed. A calculator calculates an accumulated dosage of an illuminating light irradiated onto a reticle used in a photolithography process. The calculator is connected to an exposing apparatus to expose photoresist on a semiconductor substrate. A comparator compares the calculated accumulated dosage with a preset reference dosage. When the calculated accumulated dosage is greater than or equal to the reference dosage, a controller suspends the photolithography process. Minimizing haze contamination on the reticle, thus preventing process failures.

Abstract translation: 公开了一种在曝光过程中的掩模版的管理系统和方法。 计算器计算照射到光刻工艺中使用的掩模版上的照射光的累积剂量。 计算器连接到曝光装置以暴露半导体衬底上的光致抗蚀剂。 比较器将计算的累积剂量与预设的参考剂量进行比较。 当计算的累积剂量大于或等于参考剂量时，控制器暂停光刻工艺。 最小化掩模版上的雾度污染，从而防止过程故障。

公开(公告)号：US07153370B2

公开(公告)日：2006-12-26

申请号：US11037257

申请日：2005-01-19

Applicant: Kun-tack Lee ,  Yong-pil Han ,  Sang-rok Hah

Inventor： Kun-tack Lee ,  Yong-pil Han ,  Sang-rok Hah

IPC: B08B3/00

CPC classification number: B08B3/12 ,  B08B3/08 ,  Y10S134/902

Abstract: The present application discloses a method of cleaning a semiconductor wafer by mounting a wafer to a chuck, positioning a gas guard, defining therein a chamber having an open bottom, immediately above the layer of water, spraying de-ionized water onto the wafer while rotating the chuck at a location outside the chamber when the wafer is mounted to the chuck, to thereby form a layer of water on the wafer, and spraying a cleaning gas from a gas spraying unit disposed above said chuck through the chamber and into the layer of water to thereby cause the cleaning gas to dissolve in the layer of water, and at the same time moving the chamber across a surface of the wafer, to thereby clean the wafer, wherein said gas spraying unit includes a gas injection tube oriented to inject the cleaning gas towards the wafer mounted to the chuck, and the gas guard connected to the gas injection tube.

Abstract translation: 本申请公开了一种通过将晶片安装到卡盘来清洁半导体晶片的方法，在其上方定位一个气体保护器，其中定义了一个具有开口底部的腔室，同时旋转地将去离子水喷射到晶片上 当晶片安装到卡盘上时，卡盘位于室外的位置处，从而在晶片上形成一层水，并且将来自设置在卡盘上方的气体喷射单元的清洁气体喷射通过腔室并进入 水，从而使清洁气体溶解在水层中，并且同时使腔室移动通过晶片的表面，从而清洁晶片，其中所述气体喷射单元包括朝向注射 将清洁气体朝向安装到卡盘的晶片清洁，以及连接到气体注入管的气体保护器。

公开(公告)号：US07148450B2

公开(公告)日：2006-12-12

申请号：US11250386

申请日：2005-10-17

Applicant: John Lin ,  Chau Min Chen ,  Chun Miing Hsu ,  Hui Mei Tai ,  Hsin Yi Ko ,  Chun Jen Lin ,  Chuen Yuann Liou

Inventor： John Lin ,  Chau Min Chen ,  Chun Miing Hsu ,  Hui Mei Tai ,  Hsin Yi Ko ,  Chun Jen Lin ,  Chuen Yuann Liou

IPC: G01K15/00 ,  F27D1/00 ,  F27B17/00

CPC classification number: F27B17/0016 ,  F27D19/00 ,  F27D21/0014

Abstract: The present invention discloses a portable blackbody furnace comprising a metallic body, a cylindrical cavity with a tapered end in the metallic body, a shielding plate positioned at an open end of the cylindrical cavity, at least a first heaters positioned in the shielding plate, a plurality of second heaters positioned around the metallic body, and a plurality of thermometers positioned in the metallic body. Preferably, the heat capacity of the metallic body is larger than 200 Joules/K, and has radial thickness larger than 5 mm. There are grooves formed on the outer wall of the metallic body, and the second heaters are heating wires embedded inside the grooves. In addition, the flow direction of the current between two adjacent heating wires is opposite to eliminate the magnetic field generated from the current flow.

公开(公告)号：US07129517B2

公开(公告)日：2006-10-31

申请号：US10801651

申请日：2004-03-17

Applicant: Jeong-Hwan Yang

Inventor： Jeong-Hwan Yang

IPC: H01L29/06 ,  H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01L29/785 ,  H01L21/823828 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687 ,  Y10S257/903

Abstract: To reduce a current loss through a channel and improve electron mobility, a first semiconductor layer and a second semiconductor layer (sequentially formed on a semiconductor substrate) have different lattice properties. The first semiconductor layer and the second semiconductor layer may be etched to form a first semiconductor pattern. A third semiconductor layer having a lattice property substantially identical to that of the first semiconductor layer may be formed over the first semiconductor pattern. The third semiconductor layer may then be etched to form a second semiconductor pattern. A gate may be formed on the second semiconductor pattern. The contact surface between the second semiconductor pattern and the gate pattern may consequently increased to reduce a current loss. Further, the lattice properties may be changed to improve electron mobility of the semiconductor layers.

Abstract translation: 为了减少通过沟道的电流损耗并提高电子迁移率，第一半导体层和第二半导体层（依次形成在半导体衬底上）具有不同的晶格特性。 可以蚀刻第一半导体层和第二半导体层以形成第一半导体图案。 可以在第一半导体图案之上形成具有与第一半导体层基本相同的晶格特性的第三半导体层。 然后可以蚀刻第三半导体层以形成第二半导体图案。 可以在第二半导体图案上形成栅极。 因此，可以增加第二半导体图案和栅极图案之间的接触表面以减小电流损耗。 此外，可以改变晶格特性以改善半导体层的电子迁移率。

公开(公告)号：US07126419B2

公开(公告)日：2006-10-24

申请号：US10339457

申请日：2003-01-10

Applicant: Tokio Miyasita

Inventor： Tokio Miyasita

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F3/45475 ,  H03F2203/45362 ,  H03F2203/45684

Abstract: An analog circuit includes a pair of peak-hold circuits that generate peak signals indicating the peak values of a differential pair of input signals, a first differencing circuit such as a transconductance amplifier that takes the difference between the input signal values, a second differencing circuit such as a transconductance amplifier that takes the difference between the two peak signal values, and a combining circuit such as a resistor circuit that additively combines the outputs of the differencing circuits in such a way as to compensate for direct-current offset in the input signals. Advantages of this circuit structure include reduced power consumption and simplified implementation in an integrated circuit. Low pass filters, capacitor discharging circuits, and unbalanced circuit elements can be used to obtain further advantages.

公开(公告)号：US07122486B2

公开(公告)日：2006-10-17

申请号：US10844543

申请日：2004-05-13

Applicant: Kiyohiko Toshikawa ,  Junichi Miyano

Inventor： Kiyohiko Toshikawa ,  Junichi Miyano

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76801 ,  C23C16/02 ,  C23C16/345 ,  C23C16/482 ,  H01L21/02123 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3125 ,  H01L21/318

Abstract: CVD is performed without damaging a micro-fabricated semiconductor element. An organic material gas containing amine is used as deposition material gas. The material gas is introduced into a vacuum chamber and ultraviolet light radiated from each of lamps is applied onto an object to be processed that is placed in the chamber, thereby causing chemical vapor deposition to be carried out, whereby a film is grown at a temperature such that no damage is given to a semiconductor element or the like of the object.

Abstract translation: 执行CVD而不损坏微制造的半导体元件。 使用含有有机材料的胺作为沉积材料气体。 将材料气体引入真空室中，并且将从每个灯辐射的紫外线照射到放置在室中的待处理物体上，从而进行化学气相沉积，由此在温度 使得不会对物体的半导体元件等造成损害。

公开(公告)号：US07118969B2

公开(公告)日：2006-10-10

申请号：US10787968

申请日：2004-02-27

Applicant: Jin-Kuk Chung ,  Chang-Rok Moon

Inventor： Jin-Kuk Chung ,  Chang-Rok Moon

IPC: H01L21/336

CPC classification number: H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

Abstract: A method of manufacturing a floating gate provides an enhancement for the efficiencies of electron charge and injection. First, a conductive pattern, constituting the floating gate is formed on a substrate. A first insulation layer is formed on a sidewall of the conductive pattern, and then a second insulation layer is formed at an upper portion of the conductive pattern in ways that increase the sharpness of an edge portion where the sidewall and upper portions of the conductive pattern meet. Therefore, electron transference from the floating ate to a control gate is facilitated.

Abstract translation: 制造浮栅的方法提供了电子电荷和注入效率的增强。 首先，在基板上形成构成浮栅的导电图案。 第一绝缘层形成在导电图案的侧壁上，然后在导电图案的上部形成第二绝缘层，以增加导电图案的侧壁和上部的边缘部分的锐度 遇到。 因此，易于从漂浮的电子转移到控制栅极。