发明授权
US06889348B2 Tester architecture construction data generating method, tester architecture constructing method and test circuit
失效
测试仪架构构造数据生成方法,测试仪架构构造方法和测试电路
- 专利标题: Tester architecture construction data generating method, tester architecture constructing method and test circuit
- 专利标题(中): 测试仪架构构造数据生成方法,测试仪架构构造方法和测试电路
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申请号: US09908776申请日: 2001-07-20
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公开(公告)号: US06889348B2公开(公告)日: 2005-05-03
- 发明人: Masayuki Sato
- 申请人: Masayuki Sato
- 申请人地址: JP Tokyo
- 专利权人: Renesas Technology Corporation
- 当前专利权人: Renesas Technology Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: Reed Smith LLP
- 代理商 Stanley P. Fisher, Esq.; Juan Carlos A. Marquez, Esq.
- 优先权: JP2000-231435 20000731; JP2001-203776 20010704
- 主分类号: G01R31/3181
- IPC分类号: G01R31/3181 ; G01R31/3183 ; G01R31/319 ; G06F11/22 ; G06F11/25 ; G06F11/263 ; G06F12/16 ; G06F17/50 ; G01R31/28
摘要:
The present invention provides a test circuit configuration technology suitable for use in a semiconductor device, which is capable of testing the semiconductor device without using a commercially-available tester (test device) and is less reduced in required cost. A test program related to a semiconductor device to be tested, which is described in tester language, is analyzed. Components of a test circuit (ALPG), corresponding to the contents of each test to be carried out are extracted, i.e., unwanted or unnecessary components are deleted to thereby generate the description (test circuit architecture construction data) of a circuit capable of conducting tests in desired test units according to HDL (Hardware Description Language).