发明授权
- 专利标题: Fast lock phase lock loop and method thereof
- 专利标题(中): 快锁锁相环及其方法
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申请号: US10874646申请日: 2004-06-23
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公开(公告)号: US06906565B2公开(公告)日: 2005-06-14
- 发明人: Michael F. Keaveney
- 申请人: Michael F. Keaveney
- 申请人地址: US MA Norwood
- 专利权人: Analog Devices, Inc.
- 当前专利权人: Analog Devices, Inc.
- 当前专利权人地址: US MA Norwood
- 代理机构: Iandiorio & Teska
- 主分类号: F04B
- IPC分类号: F04B20060101 ; H02M20060101 ; H03D13/00 ; H03K3/017 ; H03K3/0231 ; H03L20060101 ; H03L7/00 ; H03L7/06 ; H04B20060101
摘要:
A fast lock phase lock loop (PLL) with minimal phase disturbance when switching from wide bandwidth mode to narrow bandwidth mode including a phase frequency detector, a charge pump, a loop filter and a voltage controlled oscillator, and a sequencer circuit for, at a first time, initiating an increase in the charge pump current to increase the loop gain to widen the loop bandwidth and initiating a decrease in the resistance in the loop filter to increase the phase margin of the PLL in the wide bandwidth mode; at a second time, initiating a reduction in the charge pump current to reduce the loop gain and bandwidth, and; at a third time, initiating an increase in the resistance in the loop filter to increase the phase margin of the PLL in the narrow bandwidth mode.
公开/授权文献
- US20050030072A1 Fast lock phase lock loop and method thereof 公开/授权日:2005-02-10
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