Invention Grant
US06921672B2 Test structures and methods for inspection of semiconductor integrated circuits
有权
用于半导体集成电路检查的测试结构和方法
- Patent Title: Test structures and methods for inspection of semiconductor integrated circuits
- Patent Title (中): 用于半导体集成电路检查的测试结构和方法
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Application No.: US10338936Application Date: 2003-01-07
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Publication No.: US06921672B2Publication Date: 2005-07-26
- Inventor: Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
- Applicant: Akella V. S. Satya , Gustavo A. Pinto , David L. Adler , Robert Thomas Long , Neil Richardson , Kurt H. Weiner , David J. Walker , Lynda C. Mantalas
- Applicant Address: US CA Milpitas
- Assignee: KLA-Tencor Technologies Corporation
- Current Assignee: KLA-Tencor Technologies Corporation
- Current Assignee Address: US CA Milpitas
- Agency: Beyer, weaver & Thomas, LLP.
- Main IPC: G01N21/66
- IPC: G01N21/66 ; G01N21/95 ; G01N21/956 ; G01R31/28 ; G01R31/307 ; H01L23/544 ; H01L21/66
Abstract:
Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.
Public/Granted literature
- US20030096436A1 Test structures and methods for inspection of semiconductor integrated circuits Public/Granted day:2003-05-22
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