公开(公告)号：US08343327B2

公开(公告)日：2013-01-01

申请号：US12787330

申请日：2010-05-25

申请人： Kurt H. Weiner ,  Gaurav Verma

发明人： Kurt H. Weiner ,  Gaurav Verma

IPC分类号： C25D5/10 ,  C25D5/00 ,  C25D17/00

CPC分类号： C25D5/022 ,  C25D5/08 ,  C25D17/001 ,  C25D17/005 ,  C25D17/12

摘要： The invention relates generally to electrodeposition apparatus and methods. When depositing films via electrodeposition, where the substrate has an inherent resistivity, for example, sheet resistance in a thin film, methods and apparatus of the invention are used to electrodeposit materials onto the substrate by forming a plurality of ohmic contacts to the substrate surface and thereby overcome the inherent resistance and electrodeposit uniform films. Methods and apparatus of the invention find particular use in solar cell fabrication.

摘要翻译： 本发明一般涉及电沉积装置和方法。 当通过电沉积沉积膜时，其中衬底具有固有电阻率，例如薄膜中的薄层电阻，本发明的方法和装置用于通过在衬底表面上形成多个欧姆接触将材料电沉积到衬底上， 从而克服固有的电阻和电沉积均匀的膜。 本发明的方法和装置在太阳能电池制造中特别有用。

公开(公告)号：US08207069B2

公开(公告)日：2012-06-26

申请号：US13189894

申请日：2011-07-25

申请人： Kurt H. Weiner ,  Tony P. Chiang ,  Aaron Francis ,  John Schmidt

发明人： Kurt H. Weiner ,  Tony P. Chiang ,  Aaron Francis ,  John Schmidt

IPC分类号： H01L21/00 ,  H01L21/306 ,  C40B50/00 ,  C40B60/00

CPC分类号： C23C16/45514 ,  C23C16/45574 ,  C23C16/52 ,  H01L21/67017 ,  H01L21/67276 ,  Y10S438/907 ,  Y10S438/908 ,  Y10S438/913 ,  Y10T137/4673 ,  Y10T137/469 ,  Y10T137/87249 ,  Y10T137/87265 ,  Y10T137/87281

摘要： An integrated processing tool is described comprising a full-wafer processing module and a combinatorial processing module. Chemicals for use in the combinatorial processing module are fed from a delivery system including a set of first manifolds. An output of each first manifold is coupled to at least one mixing vessel. An output of each mixing vessel feeds more than one of a set of second manifolds. An output of each set of second manifolds feeds one of multiple site-isolated reactors of the combinatorial processing module.

摘要翻译： 描述了一种集成处理工具，其包括全晶片处理模块和组合处理模块。 用于组合处理模块的化学品从包括一组第一歧管的递送系统进料。 每个第一歧管的输出端连接至至少一个混合容器。 每个混合容器的输出馈送一组第二歧管中的多于一个。 每组第二歧管的输出馈送组合处理模块的多个位置隔离反应器中的一个。

公开(公告)号：US20070267631A1

公开(公告)日：2007-11-22

申请号：US11419174

申请日：2006-05-18

申请人： Kurt H. Weiner ,  Tony P. Chiang ,  Gustavo A. Pinto

发明人： Kurt H. Weiner ,  Tony P. Chiang ,  Gustavo A. Pinto

IPC分类号： H01L23/58

CPC分类号： H01L22/10 ,  H01L21/67005 ,  H01L22/34

摘要： The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.

摘要翻译： 本发明提供用于同时，并行和/或快速连续测试材料参数或过程结果的其它参数的系统和方法。 测试通常用于筛选不同的方法或材料以选择具有所需性质的那些方法或材料。 用于形成材料的反应器结构可以由覆盖在基板上的小的分离的反应室的阵列组成，使得基板形成每个分离的反应室的底表面。 在基板上形成测试结构，其中每个测试结构的位置对应于反应结构的分离的反应室区域。 测试结构用于测量某些参数，例如通过探测每个测试结构的接触垫，或者可以在处理期间原位进行这种测试。

公开(公告)号：US07067335B2

公开(公告)日：2006-06-27

申请号：US10264625

申请日：2002-10-02

申请人： Kurt H. Weiner ,  Gaurav Verma

发明人： Kurt H. Weiner ,  Gaurav Verma

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L22/34 ,  G01N21/9501 ,  G01R31/2644 ,  G01R31/307

摘要： An improved voltage contrast test structure is disclosed. In general terms, the test structure can be fabricated in a single photolithography step or with a single reticle or mask. The test structure includes substructures which are designed to have a particular voltage potential pattern during a voltage contrast inspection. For example, when an electron beam is scanned across the test structure, an expected pattern of intensities are produced and imaged as a result of the expected voltage potentials of the test structure. However, when there is an unexpected pattern of voltage potentials present during the voltage contrast inspection, this indicates that a defect is present within the test structure. To produce different voltage potentials, a first set of substructures are coupled to a relatively large conductive structure, such as a large conductive pad, so that the first set of substructures charges more slowly than a second set of substructures that are not coupled to the relatively large conductive structure. Mechanisms for fabricating such a test structure are also disclosed. Additionally, searching mechanisms for quickly locating defects within such a test structure, as well as other types of voltage contrast structures, during a voltage contrast inspection are also provided.

公开(公告)号：US06861666B1

公开(公告)日：2005-03-01

申请号：US10282322

申请日：2002-10-17

申请人： Kurt H. Weiner ,  Gaurav Verma ,  Peter D. Nunan ,  Indranil De

发明人： Kurt H. Weiner ,  Gaurav Verma ,  Peter D. Nunan ,  Indranil De

IPC分类号： G01R31/28 ,  G01R31/307 ,  H01L23/544 ,  H01L23/58

CPC分类号： H01L22/34 ,  G01R31/2884 ,  G01R31/307

摘要： Disclosed is test structure that can be fabricated with minimal photolithography masking steps and in which defects may be localized to specific layers. Mechanisms for fabricating such test structures are also provided. In one embodiment, a semiconductor test structure suitable for a voltage contrast inspection is provided. The test structure includes one or more test layers corresponding to one or more product layers selected from a plurality of product layers of an integrated circuit (IC) product structure. The number of the selected one or more test layers is less than a total number of the plurality of product layers of the product structure, and the test layers include at least a first portion that is designed to have a first potential during the voltage contrast inspection and a second portion that is designed to have a second potential during the voltage contrast inspection. The first potential differs from the second potential. The selected one or more test layers which correspond to product layers are selected from the plurality of product layers such that defects found in the test layers of the test structure during the voltage contrast inspection represent a prediction of defects in the corresponding product structure.

摘要翻译： 公开了可以用最小光刻掩模步骤制造并且其中缺陷可以定位于特定层的测试结构。 还提供了用于制造这种测试结构的机构。 在一个实施例中，提供了适用于电压对比度检查的半导体测试结构。 测试结构包括对应于从集成电路（IC）产品结构的多个产品层中选择的一个或多个产品层的一个或多个测试层。 所选择的一个或多个测试层的数量小于产品结构的多个产品层的总数，并且测试层至少包括设计成在电压对比度检查期间具有第一电位的第一部分 以及被设计为在电压对比度检查期间具有第二电位的第二部分。 第一个潜力与第二个潜力不同。 所选择的一个或多个对应于产品层的测试层选自多个产品层，使得在电压对比检查期间在测试结构的测试层中发现的缺陷代表相应产品结构中的缺陷的预测。

公开(公告)号：US5346850A

公开(公告)日：1994-09-13

申请号：US968561

申请日：1992-10-29

申请人： James L. Kaschmitter ,  Joel B. Truher ,  Kurt H. Weiner ,  Thomas W. Sigmon

发明人： James L. Kaschmitter ,  Joel B. Truher ,  Kurt H. Weiner ,  Thomas W. Sigmon

IPC分类号： C30B1/02 ,  H01L21/20 ,  H01L21/3215 ,  H01L29/786 ,  C30B31/20

CPC分类号： H01L29/78603 ,  C30B1/023 ,  C30B29/06 ,  H01L21/2026 ,  H01L21/32155

摘要： A method or process of crystallizing and doping amorphous silicon (a-Si) on a low-temperature plastic substrate using a short pulsed high energy source in a selected environment, without heat propagation and build-up in the substrate. The pulsed energy processing of the a-Si in a selected environment, such as BF3 and PF5, will form a doped micro-crystalline or poly-crystalline silicon (pc-Si) region or junction point with improved mobilities, lifetimes and drift and diffusion lengths and with reduced resistivity. The advantage of this method or process is that it provides for high energy materials processing on low cost, low temperature, transparent plastic substrates. Using pulsed laser processing a high (>900.degree. C.), localized processing temperature can be achieved in thin films, with little accompanying temperature rise in the substrate, since substrate temperatures do not exceed 180.degree. C. for more than a few microseconds. This method enables use of plastics incapable of withstanding sustained processing temperatures (higher than 180.degree. C.) but which are much lower cost, have high tolerance to ultraviolet light, have high strength and good transparency, compared to higher temperature plastics such as polyimide.

摘要翻译： 在选择的环境中使用短脉冲高能源在低温塑料基板上结晶和掺杂非晶硅（a-Si）的方法或工艺，而不会在衬底中积累热量。 在选择的环境中，诸如BF 3和PF 5之间的a-Si的脉冲能量处理将形成具有改善的迁移率，寿命和漂移和扩散的掺杂​​微晶或多晶硅（pc-Si）区或结点 长度和电阻率降低。 该方法或工艺的优点在于，它提供了在低成本，低温，透明塑料基材上的高能材料加工。 使用高（> 900℃）的脉冲激光加工，可以在薄膜中实现局部处理温度，基板温度升高很少，因为衬底温度不超过180℃超过几微秒。 与使用聚酰亚胺等高温塑料相比，该方法能够使用不能耐受持续的加工温度（高于180℃）的塑料，但成本低得多，对紫外线的耐受性高，强度高，透明性好。

公开(公告)号：US20110179999A1

公开(公告)日：2011-07-28

申请号：US13080441

申请日：2011-04-05

申请人： Kurt H. Weiner ,  Aaron Francis

发明人： Kurt H. Weiner ,  Aaron Francis

IPC分类号： C23C16/00

CPC分类号： H01L21/67126

摘要： Substrate processing systems and methods are described for site-isolated processing of substrates. The processing systems include numerous site-isolated reactors (SIRs). The processing systems include a reactor block having a cell array that includes numerous SIRs. A sleeve is coupled to an interior of each of the SIRs. The sleeve includes a compliance device configured to dynamically control a vertical position of the sleeve in the SIR. A sealing system is configured to provide a seal between a region of a substrate and the interior of each of the SIRs. The processing system can include numerous modules that comprise one or more site-isolated reactors (SIRs) configured for one or more of molecular self-assembly and combinatorial processing of substrates.

摘要翻译： 基板处理系统和方法被描述用于基板的场隔离处理。 处理系统包括许多场地隔离反应器（SIR）。 处理系统包括具有包括大量SIR的单元阵列的反应器块。 套筒连接到每个SIR的内部。 套筒包括配置成在SIR中动态地控制套筒的垂直位置的顺应装置。 密封系统被配置为在衬底的区域和每个SIR的内部之间提供密封。 处理系统可以包括多个模块，其包括被配置用于衬底的分子自组装和组合处理中的一个或多个的一个或多个位置隔离反应器（SIR）。

公开(公告)号：US20080156769A1

公开(公告)日：2008-07-03

申请号：US11647881

申请日：2006-12-29

申请人： Kurt H. Weiner ,  Tony P. Chiang ,  Aaron Francis ,  John Schmidt

发明人： Kurt H. Weiner ,  Tony P. Chiang ,  Aaron Francis ,  John Schmidt

IPC分类号： C23C16/00 ,  C23F1/00

CPC分类号： C23C16/45514 ,  C23C16/45574 ,  C23C16/52 ,  H01L21/67017 ,  H01L21/67276 ,  Y10S438/907 ,  Y10S438/908 ,  Y10S438/913 ,  Y10T137/4673 ,  Y10T137/469 ,  Y10T137/87249 ,  Y10T137/87265 ,  Y10T137/87281

摘要： An integrated processing tool is described comprising a full-wafer processing module and a combinatorial processing module. Chemicals for use in the combinatorial processing module are fed from a delivery system including a set of first manifolds. An output of each first manifold is coupled to at least one mixing vessel. An output of each mixing vessel feeds more than one of a set of second manifolds. An output of each set of second manifolds feeds one of multiple site-isolated reactors of the combinatorial processing module.

摘要翻译： 描述了一种集成处理工具，其包括全晶片处理模块和组合处理模块。 用于组合处理模块的化学品从包括一组第一歧管的递送系统进料。 每个第一歧管的输出端连接至至少一个混合容器。 每个混合容器的输出馈送一组第二歧管中的多于一个。 每组第二歧管的输出馈送组合处理模块的多个位置隔离反应器中的一个。

公开(公告)号：US07280945B1

公开(公告)日：2007-10-09

申请号：US10187567

申请日：2002-07-01

申请人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

发明人： Kurt H. Weiner ,  Gaurav Verma ,  Indranil De

IPC分类号： G06F17/10 ,  G06F17/50

CPC分类号： G01R31/318364

摘要： Disclosed are mechanisms are provided for determining whether a particular integrated circuit (IC) pattern is susceptible to systematic failure, e.g., due to process fluctuations. In one embodiment, final resist patterns for such IC pattern are simulated using a sparse type simulator under various process settings. The sparse type simulator uses a model (e.g., a variable threshold resist model) for a particular photolithography process in which the IC pattern is to be fabricated. The model is generated from measurements taken from a plurality of simulated structures output from a rigorous type simulator. The simulated final resist patterns may then be analyzed to determine whether the corresponding IC pattern is susceptible to systematic failure. After an IC pattern which is susceptible to systematic failure has been found, a test structure may be fabricated from a plurality of IC patterns or cells. The cells of the test structure are arranged to have a particular pattern of voltage potential or brightness levels during a voltage contrast inspection. Mechanisms for quickly inspecting such test structures to thereby predict systematic yield of a product device containing patterns similar to the test structure cells are also disclosed.

摘要翻译： 公开了提供用于确定特定集成电路（IC）模式是否易于系统故障（例如由于过程波动）的机制。 在一个实施例中，使用在各种处理设置下的稀疏型模拟器来模拟这种IC图案的最终抗蚀剂图案。 稀疏型模拟器对于要制造IC图案的特定光刻工艺使用模型（例如，可变阈值抗蚀剂模型）。 该模型是从从严格型模拟器输出的多个模拟结构中获得的测量产生的。 然后可以分析模拟的最终抗蚀剂图案，以确定相应的IC图案是否易于发生系统故障。 在已经发现容易发生系统故障的IC图案之后，可以从多个IC图案或单元制造测试结构。 测试结构的单元被布置成在电压对比度检查期间具有电压电位或亮度水平的特定图案。 还公开了用于快速检查这种测试结构从而预测包含类似于测试结构单元的图案的产品设备的系统产量的机制。

公开(公告)号：US06221726B1

公开(公告)日：2001-04-24

申请号：US08548928

申请日：1995-10-26

申请人： Kurt H. Weiner

发明人： Kurt H. Weiner

IPC分类号： H01L21336

CPC分类号： H01L22/34 ,  H01L21/223 ,  H01L21/26513 ,  H01L21/268 ,  H01L22/12

摘要： Silicon device structures designed to allow measurement of important doping process parameters immediately after the doping step has occurred. The test structures are processed through contact formation using standard semiconductor fabrication techniques. After the contacts have been formed, the structures are covered by an oxide layer and an aluminum layer. The aluminum layer is then patterned to expose the contact pads and selected regions of the silicon to be doped. Doping is then performed, and the whole structure is annealed with a pulsed excimer laser. But laser annealing, unlike standard annealing techniques, does not effect the aluminum contacts because the laser light is reflected by the aluminum. Once the annealing process is complete, the structures can be probed, using standard techniques, to ascertain data about the doping step. Analysis of the data can be used to determine probable yield reductions due to improper execution of the doping step and thus provide real-time feedback during integrated circuit fabrication.

摘要翻译： 硅器件结构设计用于在掺杂步骤发生之后立即测量重要的掺杂工艺参数。 通过使用标准半导体制造技术的接触形成来处理测试结构。 在形成接触之后，结构被氧化物层和铝层覆盖。 然后将铝层图案化以暴露待掺杂的硅的接触焊盘和选定区域。 然后进行掺杂，并且整个结构用脉冲准分子激光器退火。 但与标准退火技术不同，激光退火不影响铝触点，因为激光被铝反射。 一旦退火过程完成，可以使用标准技术探测结构以确定关于掺杂步骤的数据。 可以使用数据分析来确定由于掺杂步骤的不当执行而导致的可能的产量降低，并且因此在集成电路制造期间提供实时反馈。