发明授权
- 专利标题： System and method for wafer acceptance test configuration
- 专利标题（中）： 晶圆验收测试配置的系统和方法
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申请号： US10811190申请日： 2004-03-26
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公开(公告)号： US06929962B1公开(公告)日： 2005-08-16
- 发明人: Yung-Cheng Chang
- 申请人： Yung-Cheng Chang
- 申请人地址： TW Hsinchu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsinchu
- 代理机构： Thomas, Kayden, Horstemeyer & Risley
- 主分类号： G01R31/26
- IPC分类号： G01R31/26 ; G01R31/28 ; G05B19/418 ; H01L21/00
摘要：
A system for WAT (Wafer Acceptance Test) configuration. The system comprises an input/output device, a storage device, and a processor. The input/output device receives a first WAT model and qualification criteria. The storage device stores a preset WAT model and qualification criteria. The processor modifies the preset WAT model according to the first WAT model to generate a second WAT model, and modifies the preset qualification criteria according to the first qualification criteria to generate second qualification criteria.
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