发明授权
- 专利标题: Stacked via-stud with improved reliability in copper metallurgy
- 专利标题(中): 堆叠通孔,提高了铜冶金的可靠性
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申请号: US10306534申请日: 2002-11-27
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公开(公告)号: US06972209B2公开(公告)日: 2005-12-06
- 发明人: Birendra N. Agarwala , Conrad A. Barile , Hormazdyar M. Dalal , Brett H. Engle , Michael Lane , Ernest Levine , Xiao Hu Liu , Vincent McGahay , John F. McGrath , Conal E. Murray , Jawahar P. Nayak , Du B. Nguyen , Hazara S. Rathore , Thomas M. Shaw
- 申请人: Birendra N. Agarwala , Conrad A. Barile , Hormazdyar M. Dalal , Brett H. Engle , Michael Lane , Ernest Levine , Xiao Hu Liu , Vincent McGahay , John F. McGrath , Conal E. Murray , Jawahar P. Nayak , Du B. Nguyen , Hazara S. Rathore , Thomas M. Shaw
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Scully, Scott, Murphy & Presser
- 代理商 Robert M. Trepp, Esq.
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L23/522 ; H01L23/532 ; H01L21/00
摘要:
A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.