摘要:
In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.
摘要:
A capacitor having a multilevel interconnection technology and process thereof. Also disclosed is a process of electrically connecting a capacitor to an object, comprising the steps of first obtaining a capacitor. At least one solder ball is reflowed and secured onto the capacitor. The solder ball is in electrical communication with the capacitor through a contacting means. On this reflowed solder ball a cap of low melting point metal is secured. This can be done in a number of ways. The preferred way is to positioning a mask over the solder ball such that a portion of the solder ball is exposed through openings in the mask. At least one layer of a low melting point metal is deposited on the exposed surface of the solder ball through the mask, and thereby forming a capacitor with a multilevel interconnect cap. The low melting point metal can interact with the surface of the solder ball to form a cap of an eutectic or a liquefied portion. The cap portion can then be joined to the object.
摘要:
The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.
摘要:
A method of providing interconnections to a semiconductor integrated chip designed to eliminate electromigration. The method includes the steps of forming an interconnection with segments of Al interspersed with segments of a refractory metal, wherein each aluminum segments is followed by a segment of refractory metal, aligning the aluminum and refractory metal segments with respect to each other ensuring electrical continuity.
摘要:
A device includes a substrate, at least one dielectric layer positioned on said substrate, and metalization positioned in an opening in the at least one dielectric layer and extending a predetermined distance towards the substrate from a surface which is substantially coplanar with a surface of the at least one dielectric layer. The metalization includes a low resistivity metal or alloy encapsulated by a refractory metal or alloy having a resistivity greater than that of the low resistivity metal or alloy and having a columnar structure. The metalization has a plurality of sides in cross-section, at least three sides of the plurality of sides being substantially formed of a refractory metal or alloy having a common composition, at least two sides of the plurality of sides extending substantially the predetermined distance, and all of the plurality of sides being formed within the opening in the at least one dielectric layer.
摘要:
A contact structure for a semiconductor device having a first refractory metal layer formed only at the bottom of a contact hole. The first refractory metal is selected from a group comprising titanium (Ti), titanium alloys or compounds such as Ti/TiN, tungsten (W), titanium/tungsten (Ti/W) alloys, or chromium (Cr) or tantalum (Ta) and their alloys or some other suitable material. A low resistivity layer comprising a single, binary or ternary metalization is deposited over the first refractory metal layer in the contact hole by a method such as PVD using evaporation or collimated sputtering. The low resistivity layer has side walls which taper inwardly toward one another with increasing height of the layer and the low resistivity layer does not contact the side walls of the contact hole. The low resistivity layer may be Al.sub.x Cu.sub.y (x+y=1; x.gtoreq.0, y.gtoreq.0), ternary alloys such as Al-Pd-Cu or multicomponent alloys such as Al-Pd-Nb-Au. A second refractory metal layer is deposited over the low resistivity layer. The second refractory metal layer may be tungsten, cobalt, nickel, molybdenum or alloys/compounds such as Ti/TiN. The first and second refractory metal layers completely encapsulate the low resistivity layer. The first and second refractory metal layers can comprise an alloy containing silicon with a higher incorporated silicon content near the top of the contact hold present as a distinct or graded composition than at a location closer to the bottom of the contact hole.
摘要:
In one embodiment, a semiconductor device is formed to include a plurality of conductor layers that interconnect electrical signals between semiconductor elements of the semiconductor device. A metal shield layer is formed overlying a portion of the plurality of conductor layers. A signal re-distribution layer is formed overlying the metal shield layer.
摘要:
A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with hafnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper interstitial positions.
摘要:
The present invention relates generally to a new sequence of methods and materials to improve the process yield and to enhance the reliability of multilevel interconnection with sub-half-micron geometry by making judicious use of composite insulators to prevent metal thinning over hard metal via plugs and by preventing process induced metal spike formation. The method takes advantage of the double damascene process. The metal spikes and the metal thinning resulting from over etch process is prevented in this method by using a pair of insulators which require different chemistries for etching.
摘要:
A structure and method is disclosed for directly attaching a device or package on flexible organic circuit carriers having low cost and high reliability. IC chips with a new solder interconnect structure, comprised of a layer of pure tin, deposited on the top of high melting Pb--Sn solder balls are employed for joining. These methods, techniques and metallurgical structures enables direct attachment of electronic devices of any complexity to any substrate and to any level of packaging hierarchy. Also, devices or packages having other joining technologies, eg. SMT, BGA, TBGA, etc. could be joined onto the flexible circuit carrier.