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公开(公告)号：US06972209B2
公开(公告)日：2005-12-06
申请号：US10306534
申请日：2002-11-27
申请人： Birendra N. Agarwala , Conrad A. Barile , Hormazdyar M. Dalal , Brett H. Engle , Michael Lane , Ernest Levine , Xiao Hu Liu , Vincent McGahay , John F. McGrath , Conal E. Murray , Jawahar P. Nayak , Du B. Nguyen , Hazara S. Rathore , Thomas M. Shaw
发明人： Birendra N. Agarwala , Conrad A. Barile , Hormazdyar M. Dalal , Brett H. Engle , Michael Lane , Ernest Levine , Xiao Hu Liu , Vincent McGahay , John F. McGrath , Conal E. Murray , Jawahar P. Nayak , Du B. Nguyen , Hazara S. Rathore , Thomas M. Shaw
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/00
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76829 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , Y10T428/24917 , H01L2924/00
摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.
摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。
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2.发明授权公开(公告)号：US08053257B2
公开(公告)日：2011-11-08
申请号：US12061104
申请日：2008-04-02
申请人： Kaushik Chanda , Hazara S. Rathore , Paul S. McLaughlin , Robert D. Edwards , Lawrence A. Clevenger , Andrew P. Cowley , Chih-Chao Yang , Conrad A. Barile
发明人： Kaushik Chanda , Hazara S. Rathore , Paul S. McLaughlin , Robert D. Edwards , Lawrence A. Clevenger , Andrew P. Cowley , Chih-Chao Yang , Conrad A. Barile
IPC分类号： H01L21/00
CPC分类号： G06F17/5009 , G01R31/287 , G06F2217/10 , G06F2217/70 , G06F2217/78
摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for a layer within chips comprising a semiconductor wafer lot. If only one mode is calculated, that is the best calculated mode. If multiple modes can be calculated, a best mode that most accurately represents dielectric breakdown for the semiconductor wafer lot is determined. Premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation from the best calculated mode.
摘要翻译： 本发明预测半导体中的过早的介质击穿。 对包括半导体晶片批次的芯片内的层计算至少一个介电击穿模式。 如果只计算一种模式，那就是最好的计算模式。 如果可以计算多种模式，则确定最准确地代表半导体晶片批次的绝缘击穿的最佳模式。 过早的介质击穿将与任何具有小于最佳计算模式的预定标准偏差的击穿电压的半导体相关联。
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3.发明申请公开(公告)号：US20080174334A1
公开(公告)日：2008-07-24
申请号：US12061104
申请日：2008-04-02
申请人： Kaushik Chanda , Hazara S. Rathore , Paul S. McLaughlin , Robert D. Edwards , Lawrence A. Clevenger , Andrew P. Cowley , Chih-Chao Yang , Conrad A. Barile
发明人： Kaushik Chanda , Hazara S. Rathore , Paul S. McLaughlin , Robert D. Edwards , Lawrence A. Clevenger , Andrew P. Cowley , Chih-Chao Yang , Conrad A. Barile
CPC分类号： G06F17/5009 , G01R31/287 , G06F2217/10 , G06F2217/70 , G06F2217/78
摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.
摘要翻译： 本发明预测半导体中的过早的介质击穿。 对于半导体晶片计算至少一个介电击穿模式。 如果计算一种模式，则过早的介电击穿将与在所述计算模式中具有小于多个击穿电压的预定标准偏差的击穿电压的任何半导体相关联。 如果计算多个模式，则确定最准确地代表半导体晶片的电介质击穿的模式，并且过早的电介质击穿将与任何具有小于计算模式的预定标准的击穿电压的半导体相关联，其最准确地表示用于 半导体晶片。
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公开(公告)号：US4243435A
公开(公告)日：1981-01-06
申请号：US51078
申请日：1979-06-22
IPC分类号： H01L29/73 , H01L21/033 , H01L21/265 , H01L21/331 , H01L21/76 , H01L21/8222 , H01L27/06 , H01L27/07 , H01L29/417 , H01L21/22 , H01L21/26
CPC分类号： H01L27/0766 , H01L21/033 , H01L27/0664 , Y10S148/139
摘要： A very high current ion implanted emitter is formed in a diffused base. Windows are made through the silicon nitride and silicon dioxide layes to both the base contact and the emitter regions using a resist mask. These regions are then protected by resist and the collector contact window is opened through the remainder of the silicon dioxide layer to the reach through region. A screen oxide is then grown in all the exposed areas after the removal of the resist mask. A resist mask is applied which covers only the base and Schottky anode regions. Arsenic is then implanted through the exposed screened areas followed by an etch back step to remove the top damaged layer. With some remaining screen oxide serving as a cap, the emitter drive-in is done.
摘要翻译： 在扩散的基底中形成非常高的电流离子注入发射体。 Windows通过氮化硅和二氧化硅制成，使用抗蚀剂掩模层叠到基极接触和发射极区两者。 然后这些区域被抗蚀剂保护，并且集电极接触窗口通过二氧化硅层的其余部分打开到达通过区域。 然后在去除抗蚀剂掩模之后，在所有曝光区域中生长屏幕氧化物。 应用仅覆盖基极和肖特基阳极区的抗蚀剂掩模。 然后通过暴露的筛选区域植入砷，然后通过回蚀步骤去除顶部损伤层。 使用一些剩余的屏幕氧化物作为盖子，发射器驱动完成。
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5.发明授权Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps 失效通过离子注入和扩散步骤的组合形成集成电路区域的方法
公开(公告)号：US4060427A
公开(公告)日：1977-11-29
申请号：US673314
申请日：1976-04-05
IPC分类号： H01L21/306 , H01L21/033 , H01L21/22 , H01L21/223 , H01L21/265 , H01L21/266 , H01L21/331 , H01L29/73 , H01L21/324
CPC分类号： H01L21/033 , H01L21/223 , H01L21/266 , Y10S148/131 , Y10S148/143 , Y10S438/965
摘要： A region in an integrated circuit substrate is formed by first ion implanting impurities of a selected conductivity-determining type into a semiconductor substrate through at least one aperture in a masking electrically insulative layer, and then diffusing a conductivity-determining impurity of the same type through the same aperture into said substrate.The method has particular application when the electrically insulative layer is a composite of two layers, e.g., a top layer of silicon nitride and a bottom layer of silicon dioxide and the aperture is thus a pair of registered openings respectively through said silicon nitride and silicon dioxide layers, and the aperture through the silicon dioxide layer has greater lateral dimensions than that in the silicon nitride layer to provide an undercut beneath the silicon nitride ion implantation barrier layer.
摘要翻译： 集成电路衬底中的区域通过首先通过掩模电绝缘层中的至少一个孔将选择的导电性确定类型的杂质注入到半导体衬底中，然后通过相同类型的导电性确定杂质扩散 相同的孔进入所述基底。
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