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    Stacked via-stud with improved reliability in copper metallurgy
    1.
    发明授权
    Stacked via-stud with improved reliability in copper metallurgy 失效
    堆叠通孔，提高了铜冶金的可靠性

    公开(公告)号：US06972209B2

    公开(公告)日：2005-12-06

    申请号：US10306534

    申请日：2002-11-27

    申请人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

    发明人： Birendra N. Agarwala ,  Conrad A. Barile ,  Hormazdyar M. Dalal ,  Brett H. Engle ,  Michael Lane ,  Ernest Levine ,  Xiao Hu Liu ,  Vincent McGahay ,  John F. McGrath ,  Conal E. Murray ,  Jawahar P. Nayak ,  Du B. Nguyen ,  Hazara S. Rathore ,  Thomas M. Shaw

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/00

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

    摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

    摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。

    Stacked via-stud with improved reliability in copper metallurgy
    2.
    发明申请
    Stacked via-stud with improved reliability in copper metallurgy 审中-公开
    堆叠通孔，提高了铜冶金的可靠性

    公开(公告)号：US20060014376A1

    公开(公告)日：2006-01-19

    申请号：US11230841

    申请日：2005-09-20

    申请人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

    发明人： Birendra Agarwala ,  Conrad Barile ,  Hormazdyar Dalal ,  Brett Engel ,  Michael Lane ,  Ernest Levine ,  Xiao Liu ,  Vincent McGahay ,  John McGrath ,  Conal Murray ,  Jawahar Nayak ,  Du Nguyen ,  Hazara Rathore ,  Thomas Shaw

    IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L21/31

    CPC分类号： H01L23/53295 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76838 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10T428/24917 ,  H01L2924/00

    摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.

    摘要翻译： 一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。 多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。 在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织 互连级别，从而增加互连级别之间堆叠通孔的灵活性。