- 专利标题： Nonplanar device with stress incorporation layer and method of fabrication
-
申请号： US10834717申请日： 2004-04-28
-
公开(公告)号： US06974738B2公开(公告)日： 2005-12-13
- 发明人: Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta
- 申请人： Scott A. Hareland , Robert S. Chau , Brian S. Doyle , Suman Datta
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor and Zafman
- 主分类号： H01L21/336
- IPC分类号： H01L21/336 ; H01L29/10 ; H01L29/423 ; H01L29/76 ; H01L29/786 ; H01L21/8238
摘要：
A semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls is formed on an insulating substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and is formed adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. A thin film is then formed adjacent to the semiconductor body wherein the thin film produces a stress in the semiconductor body.
公开/授权文献
信息查询
IPC分类:
