发明授权
US06979851B2 Structure and method of vertical transistor DRAM cell having a low leakage buried strap
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具有低泄漏掩埋带的垂直晶体管DRAM单元的结构和方法
- 专利标题: Structure and method of vertical transistor DRAM cell having a low leakage buried strap
- 专利标题(中): 具有低泄漏掩埋带的垂直晶体管DRAM单元的结构和方法
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申请号: US10265558申请日: 2002-10-04
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公开(公告)号: US06979851B2公开(公告)日: 2005-12-27
- 发明人: Dureseti Chidambarrao , Jack Allan Mandelman , Carl John Radens
- 申请人: Dureseti Chidambarrao , Jack Allan Mandelman , Carl John Radens
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 主分类号: G11C11/24
- IPC分类号: G11C11/24 ; H01L21/8242 ; H01L29/76
摘要:
A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.
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