发明授权
US06996736B1 Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit
有权
可编程时钟网络，用于将时钟信号分配到集成电路的第一和第二部分之间和之间
- 专利标题： Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuit
- 专利标题（中）： 可编程时钟网络，用于将时钟信号分配到集成电路的第一和第二部分之间和之间
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申请号： US10076172申请日： 2002-02-12
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公开(公告)号： US06996736B1公开(公告)日： 2006-02-07
- 发明人: Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
- 申请人： Triet Nguyen , David Jefferson , Srinivas Reddy , Keone Streicher
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Townsend and Townsend and Crew LLP
- 主分类号： G06F1/10
- IPC分类号： G06F1/10
摘要：
A clock network for an integrated circuits includes a first set of lines configured to distribute clock signals to a first section of the integrated circuit. The clock network also includes a second set of lines configured to distribute clock signals to a second section of the integrated circuit separately from the first section of the integrated circuit.
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