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    Flexible I/O routing resources
    4.
    发明授权
    Flexible I/O routing resources 有权
    灵活的I / O路由资源

    公开(公告)号：US06826741B1

    公开(公告)日：2004-11-30

    申请号：US10289629

    申请日：2002-11-06

    申请人： Brian D. Johnson ,  Andy L. Lee ,  Cameron McClintock ,  Triet Nguyen ,  David Jefferson ,  Paul Leventis ,  David Lewis ,  Vaughn Betz ,  Michael Chan

    发明人： Brian D. Johnson ,  Andy L. Lee ,  Cameron McClintock ,  Triet Nguyen ,  David Jefferson ,  Paul Leventis ,  David Lewis ,  Vaughn Betz ,  Michael Chan

    IPC分类号： G06F1750

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.

    摘要翻译： 在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。 在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由， 可能包括I / O到核心，核到I / O和核心到核心的路由。 在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。 在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。 在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

    Line segmentation in programmable logic devices having redundancy circuitry
    5.
    发明授权
    Line segmentation in programmable logic devices having redundancy circuitry 有权
    具有冗余电路的可编程逻辑器件中的线分割

    公开(公告)号：US06759871B2

    公开(公告)日：2004-07-06

    申请号：US10422007

    申请日：2003-04-22

    申请人： Triet Nguyen ,  Changsong Zhang ,  David Jefferson

    发明人： Triet Nguyen ,  Changsong Zhang ,  David Jefferson

    IPC分类号： H03K19177

    CPC分类号： H03K19/17764 ,  G11C29/70 ,  H03K19/17728 ,  H03K19/17736

    摘要： Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.

    摘要翻译： 用于在具有冗余电路的可编程逻辑器件中分割线路的方法和装置。 可编程逻辑器件包括第一多个逻辑阵列块。 第一多个逻辑阵列块包括第一逻辑阵列块和第二逻辑阵列块，耦合到分段缓冲器的第一可编程互连线并且可编程地耦合到第一逻辑阵列块，以及耦合到分段的第二可编程互连线 缓冲器并且可编程地耦合到第二逻辑阵列块。 分段缓冲器能够选择性地在第一可编程互连线和第二可编程互连线之间提供开路，缓冲器驱动从第一可编程互连线到第二可编程互连线的信号，或者来自第二可编程互连线的缓冲器驱动信号 互连线到第一可编程互连线。

    Line segmentation in programmable logic devices having redundancy circuitry
    6.
    发明授权
    Line segmentation in programmable logic devices having redundancy circuitry 有权

    公开(公告)号：US06600337B2

    公开(公告)日：2003-07-29

    申请号：US09844077

    申请日：2001-04-26

    申请人： Triet Nguyen ,  Changsong Zhang ,  David Jefferson

    发明人： Triet Nguyen ,  Changsong Zhang ,  David Jefferson

    IPC分类号： H03K19177

    CPC分类号： H03K19/17764 ,  G11C29/70 ,  H03K19/17728 ,  H03K19/17736

    摘要： Methods and apparatus for segmenting lines in programmable logic devices having redundancy circuitry. A programmable logic device includes a first plurality of logic array blocks. The first plurality of logic array blocks includes a first logic array block and a second logic array block, a first programmable interconnect line coupled to a segmentation buffer and programmably coupled to the first logic array block, and a second programmable interconnect line coupled to the segmentation buffer and programmably coupled to the second logic array block. The segmentation buffer is capable of selectively providing an open circuit between the first programmable interconnect line and the second programmable interconnect line, a buffer driving signals from the first programmable interconnect line to the second programmable interconnect line, or a buffer driving signals from the second programmable interconnect line to the first programmable interconnect line.