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US07028277B2 Process related deviation corrected parasitic capacitance modeling method 失效
过程相关偏差纠正寄生电容建模方法

Process related deviation corrected parasitic capacitance modeling method
Abstract:
Each of a method for determining a parasitic capacitance and an apparatus for determining the parasitic capacitance provides for an experimental correlation within a parasitic capacitance model of a series of conductor layer nominal dimensions and spacings with a process related deviation to provide a series of conductor layer actual dimensions and spacings. The method and the apparatus further provide for determining the parasitic capacitance while employing the conductor layer actual dimensions and spacings. The parasitic capacitance is thus determined with enhanced accuracy.
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