Invention Grant
- Patent Title: Process related deviation corrected parasitic capacitance modeling method
- Patent Title (中): 过程相关偏差纠正寄生电容建模方法
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Application No.: US10326500Application Date: 2002-12-20
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Publication No.: US07028277B2Publication Date: 2006-04-11
- Inventor: Victor C. Y. Chang , Chung-Shi Chiang , Chien-Wen Chen , Harry Chuang , Hsin-Yi Lee , Yu-Tai Chia
- Applicant: Victor C. Y. Chang , Chung-Shi Chiang , Chien-Wen Chen , Harry Chuang , Hsin-Yi Lee , Yu-Tai Chia
- Applicant Address: JP Hsin Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: JP Hsin Chu
- Agency: Tung & Assoc
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45

Abstract:
Each of a method for determining a parasitic capacitance and an apparatus for determining the parasitic capacitance provides for an experimental correlation within a parasitic capacitance model of a series of conductor layer nominal dimensions and spacings with a process related deviation to provide a series of conductor layer actual dimensions and spacings. The method and the apparatus further provide for determining the parasitic capacitance while employing the conductor layer actual dimensions and spacings. The parasitic capacitance is thus determined with enhanced accuracy.
Public/Granted literature
- US20040123257A1 Process related deviation corrected parasitic capacitance modeling method Public/Granted day:2004-06-24
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