公开(公告)号：US07028277B2

公开(公告)日：2006-04-11

申请号：US10326500

申请日：2002-12-20

申请人： Victor C. Y. Chang ,  Chung-Shi Chiang ,  Chien-Wen Chen ,  Harry Chuang ,  Hsin-Yi Lee ,  Yu-Tai Chia

发明人： Victor C. Y. Chang ,  Chung-Shi Chiang ,  Chien-Wen Chen ,  Harry Chuang ,  Hsin-Yi Lee ,  Yu-Tai Chia

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036

摘要： Each of a method for determining a parasitic capacitance and an apparatus for determining the parasitic capacitance provides for an experimental correlation within a parasitic capacitance model of a series of conductor layer nominal dimensions and spacings with a process related deviation to provide a series of conductor layer actual dimensions and spacings. The method and the apparatus further provide for determining the parasitic capacitance while employing the conductor layer actual dimensions and spacings. The parasitic capacitance is thus determined with enhanced accuracy.

摘要翻译： 用于确定寄生电容的方法和用于确定寄生电容的装置中的每一个提供了在一系列导体层标称尺寸和间隔的寄生电容模型内的与过程相关偏差的实验相关性，以提供一系列导体层实际 尺寸和间距。 该方法和装置进一步提供了在采用导体层的实际尺寸和间距的同时确定寄生电容。 因此，寄生电容的精度提高。

公开(公告)号：US06800496B1

公开(公告)日：2004-10-05

申请号：US10644322

申请日：2003-08-20

申请人： Chung-Shi Chiang ,  Ke-Wei Su ,  Chung-Kai Lin ,  Jaw-Kang Her ,  Yu-Tai Chia

发明人： Chung-Shi Chiang ,  Ke-Wei Su ,  Chung-Kai Lin ,  Jaw-Kang Her ,  Yu-Tai Chia

IPC分类号： G01R3126

CPC分类号： G01R31/2621 ,  G01R31/27 ,  G01R31/2831

摘要： A method of characterizing gate leakage current in the fabrication of integrated circuits is described. A MOSFET model is provided including a gate electrode deposed over a gate oxide layer on a substrate and source and drain regions associated with the gate electrode. Device current is measured at four terminals simultaneously wherein one of the terminals is a drain terminal. The other terminals are the source, gate, and substrate. The portion of the device current measured at the drain terminal that is contributed by gate current is evaluated. The evaluated gate current contribution is subtracted from the drain terminal current measurement to obtain pure drain current. Fitting procedures are performed to obtain curves for the device currents. The pure drain current is used to extract mobility model parameters.

摘要翻译： 描述了在集成电路的制造中表征栅极漏电流的方法。 提供了一种MOSFET模型，其包括位于衬底上的栅极氧化物层上的栅电极以及与栅电极相关联的源区和漏区。 在四个端子同时测量器件电流，其中一个端子是漏极端子。 其他端子是源极，栅极和衬底。 评估在漏极端子处测量的由栅极电流贡献的器件电流部分。 从漏极端子电流测量中减去所评估的栅极电流贡献，以获得纯漏极电流。 执行拟合程序以获得器件电流的曲线。 纯漏电流用于提取移动模型参数。

公开(公告)号：US20050023639A1

公开(公告)日：2005-02-03

申请号：US10632456

申请日：2003-07-31

申请人： Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

发明人： Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

IPC分类号： H01L21/02 ,  H01L27/08 ,  H01L29/00

CPC分类号： H01L28/10 ,  H01L27/08

摘要： An inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type and at least two deep wells of opposite conductivity type in the substrate underneath the track. In another embodiment, an inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type; a shallow trench isolation region formed in the substrate underneath the trace; and at least two deep wells of opposite conductivity type in the substrate underneath the shallow trench isolation region. The present invention also includes methods of manufacturing the aforementioned inductors.

摘要翻译： 集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在轨道下方的衬底中的第一导电类型的半导体衬底和相反导电类型的至少两个深阱。 在另一个实施例中，集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在第一导电类型的半导体衬底上; 在轨迹下方的衬底中形成的浅沟槽隔离区域; 以及在浅沟槽隔离区域下方的衬底中具有相反导电类型的至少两个深阱。 本发明还包括制造上述电感器的方法。

公开(公告)号：US06989578B2

公开(公告)日：2006-01-24

申请号：US10632456

申请日：2003-07-31

申请人： Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

发明人： Tzu-Jin Yeh ,  Hsien-Chang Wu ,  Ming-Ta Yang ,  Yu-Tai Chia

IPC分类号： H01L29/41

CPC分类号： H01L28/10 ,  H01L27/08

摘要： An inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type and at least two deep wells of opposite conductivity type in the substrate underneath the track. In another embodiment, an inductor in an integrated circuit comprises a conductive trace disposed over an insulating layer which overlies a semiconductor substrate of a first conductivity type; a shallow trench isolation region formed in the substrate underneath the trace; and at least two deep wells of opposite conductivity type in the substrate underneath the shallow trench isolation region. The present invention also includes methods of manufacturing the aforementioned inductors.

摘要翻译： 集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在轨道下方的衬底中的第一导电类型的半导体衬底和相反导电类型的至少两个深阱。 在另一个实施例中，集成电路中的电感器包括布置在绝缘层上的导电迹线，绝缘层覆盖在第一导电类型的半导体衬底上; 在轨迹下方的衬底中形成的浅沟槽隔离区域; 以及在浅沟槽隔离区域下方的衬底中具有相反导电类型的至少两个深阱。 本发明还包括制造上述电感器的方法。

公开(公告)号：US20050206957A1

公开(公告)日：2005-09-22

申请号：US10804540

申请日：2004-03-19

申请人： Yu-Tai Chia ,  Tse-Lun Tsai ,  Chung-Lun Kuo ,  Shiun-Huan Lai

发明人： Yu-Tai Chia ,  Tse-Lun Tsai ,  Chung-Lun Kuo ,  Shiun-Huan Lai

IPC分类号： G06F15/00 ,  G06F17/22 ,  G06F17/24

CPC分类号： G06F17/248 ,  G06F17/2288

摘要： A computer-based system and method for generating a primary document characterizing a device from multiple secondary documents is provided. In one example, the method includes defining a primary document template and multiple input files. Each input file defines the source and type of information for a section of the primary document template. A document generation engine parses the secondary documents and inserts information from them into the primary document template based on the input files. After the primary document is generated, related technologies or devices may be identified and notified of changes to the device in the primary document. The related technologies or devices may then be updated if desired.

摘要翻译： 提供了一种用于从多个次要文档生成表征设备的主要文档的基于计算机的系统和方法。 在一个示例中，该方法包括定义主文档模板和多个输入文件。 每个输入文件定义主文档模板部分的信息源和类型。 文档生成引擎解析辅助文档，并根据输入文件将信息插入到主文档模板中。 在生成主文档之后，可以识别相关技术或设备并通知主文档中对设备的更改。 如果需要，可以更新相关的技术或设备。

公开(公告)号：US07469376B2

公开(公告)日：2008-12-23

申请号：US10804540

申请日：2004-03-19

申请人： Yu-Tai Chia ,  Tse-Lun Tsai ,  Chung-Lun Kuo ,  Shiun-Huan Lai

发明人： Yu-Tai Chia ,  Tse-Lun Tsai ,  Chung-Lun Kuo ,  Shiun-Huan Lai

IPC分类号： G06F17/00

CPC分类号： G06F17/248 ,  G06F17/2288

摘要： A computer-based system and method for generating a primary document characterizing a device from multiple secondary documents is provided. In one example, the method includes defining a primary document template and multiple input files. Each input file defines the source and type of information for a section of the primary document template. A document generation engine parses the secondary documents and inserts information from them into the primary document template based on the input files. After the primary document is generated, related technologies or devices may be identified and notified of changes to the device in the primary document. The related technologies or devices may then be updated if desired.

摘要翻译： 提供了一种用于从多个次要文档生成表征设备的主要文档的基于计算机的系统和方法。 在一个示例中，该方法包括定义主文档模板和多个输入文件。 每个输入文件定义主文档模板部分的信息源和类型。 文档生成引擎解析辅助文档，并根据输入文件将信息插入到主文档模板中。 在生成主文档之后，可以识别相关技术或设备并通知主文档中对设备的更改。 如果需要，可以更新相关的技术或设备。

公开(公告)号：US06819542B2

公开(公告)日：2004-11-16

申请号：US10379121

申请日：2003-03-04

申请人： Tse-Lun Tsai ,  Yu-Tai Chia ,  JC Guo

发明人： Tse-Lun Tsai ,  Yu-Tai Chia ,  JC Guo

IPC分类号： H01G4012

CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L2924/0002 ,  Y10T29/435 ,  H01L2924/00

摘要： A capacitor has at least two layers of substantially parallel interdigitated strips. The strips of each layer are alternately connected to a first and a second bus. The first and second buses of each layer are interconnected to first and second buses of an adjacent layer. The strips of each layer are approximately perpendicular to strips of an adjacent layer. The capacitor further includes dielectric material between strips of the same and different layers. A method of fabricating the capacitor includes forming at least two layers of substantially parallel interdigitated strips which are alternately connected to first and second buses of each layer. The buses of each layer are connected to the respective buses of an adjacent layer. The strips of one layer are approximately perpendicular to the strips of an adjacent layer. Dielectric material is formed between strips of the same and different layers.

摘要翻译： 电容器具有至少两层基本上平行的叉指条。 每层的条带交替地连接到第一和第二总线。 每层的第一和第二总线与相邻层的第一和第二总线相互连接。 每层的条带大致垂直于相邻层的条带。 电容器还包括相同层和不同层的条之间的介电材料。 一种制造电容器的方法包括形成至少两层基本上平行的交叉指状的条，其交替地连接到每层的第一和第二总线。 每层的总线连接到相邻层的相应总线。 一层的条带大致垂直于相邻层的条带。 电介质材料形成在相同层和不同层的条之间。