Invention Grant
- Patent Title: Reduced-hardware soft error detection
- Patent Title (中): 降低硬件软错误检测
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Application No.: US10228432Application Date: 2002-08-27
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Publication No.: US07035891B2Publication Date: 2006-04-25
- Inventor: Sivakumar Makineni , Gautam B. Doshi
- Applicant: Sivakumar Makineni , Gautam B. Doshi
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Shireen I. Bacon
- Main IPC: G06F11/16
- IPC: G06F11/16

Abstract:
A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.
Public/Granted literature
- US20040044717A1 Reduced-hardware soft error detection Public/Granted day:2004-03-04
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