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公开(公告)号：US07035891B2
公开(公告)日：2006-04-25
申请号：US10228432
申请日：2002-08-27
IPC分类号： G06F11/16
CPC分类号： G06F11/0751 , G06F11/0721
摘要： A method and system are provided for performing soft error detection for integer addition and subtraction operations without the use of redundant logic. For integer addition and subtraction, compensate logic produces a compensate value utilizing arithmetic logic unit (ALU) result and operands. The compensate value is validated by the validate logic against a predetermined value to determine whether a soft error has occurred. Such compensate logic and validate logic operate on the integer operands and on the result produced by the ALU without redundant carry-propagate hardware.
摘要翻译： 提供了一种方法和系统，用于在不使用冗余逻辑的情况下执行整数加减运算的软错误检测。 对于整数加法和减法，补偿逻辑利用算术逻辑单元（ALU）结果和操作数产生补偿值。 补偿值由验证逻辑针对预定值确认，以确定是否发生软错误。 这种补偿逻辑和验证逻辑对整数操作数和ALU产生的结果无冗余的进位传播硬件进行操作。
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公开(公告)号：US06292886B1
公开(公告)日：2001-09-18
申请号：US09169865
申请日：1998-10-12
IPC分类号： G06F1716
CPC分类号： G06F9/3885 , G06F9/30014 , G06F9/30036 , G06F9/3893
摘要： A system for processing SIMD operands in a packed data format includes a scalar FMAC and a vector FMAC coupled to a register file through an operand delivery module. For vector operations, the operand delivery module bit steers a SIMD operand of the packed operand into an unpacked operand for processing by the first execution unit. Another SIMD operand is processed by the vector execution unit.
摘要翻译： 用于以打包数据格式处理SIMD操作数的系统包括标量FMAC和通过操作数传送模块耦合到寄存器文件的向量FMAC。 对于向量操作，操作数传送模块位将打包操作数的SIMD操作数转换为解包操作数，以供第一执行单元处理。 另一个SIMD操作数由向量执行单元处理。
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公开(公告)号：US5793654A
公开(公告)日：1998-08-11
申请号：US719835
申请日：1996-09-30
CPC分类号： G06F5/012
摘要： A saturating alignment shifter for use in the multiply and accumulate unit in a floating point arithmetic unit of a microprocessor that mimics the ideal model of an infinitely wide shifter. A saturation alignment shifter is provided that, in the case of the operation of A*B.+-.C, saturates at a predetermined shifting increment and, in the case where the mantissa of C is saturated, places the mantissa C in the left most significant bits. After adding C to A*B in a summation unit, the mantissa of A*B ends up in the right most significant bits and a single intervening bit, termed the bubble bit, remains between the mantissa of C and the mantissa of A*B. The bubble bit acts to mimic any intervening bits that would have occurred in the case of an ideal infinitely wide shifter. The new shifter eliminates hardware required for special cases and treats all operations with a single alignment shifter giving a system that is faster and more simple than conventional systems.
摘要翻译： 一种饱和对准移位器，用于微处理器的浮点算术单元中的乘法和累积单元，该微处理器模拟无限宽移位器的理想模型。 提供饱和对准移位器，在A * B +/- C的操作的情况下，以预定的移动增量饱和，并且在C的尾数饱和的情况下，将尾数C置于最左侧 位。 在求和单元中向A * B添加C之后，A * B的尾数最终在最右边的最高有效位，并且称为气泡位的单个中间位保留在C的尾数与A * B的尾数之间 。 气泡位用于模拟在理想的无限宽移位器的情况下将发生的任何中间位。 新的移位器消除了特殊情况下所需的硬件，并使用单个对准移位器处理所有操作，给出比传统系统更快更简单的系统。
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4.发明授权Method for setting a bit associated with each component of packed floating-pint operand that is normalized in SIMD operations 有权用于设置与在SIMD操作中归一化的打包浮点型操作数的每个组件相关联的位的方法公开(公告)号：US06321327B1
公开(公告)日：2001-11-20
申请号：US09223457
申请日：1998-12-30
IPC分类号： G06F738
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30105 , G06F9/30109 , G06F9/30192
摘要： A method is provided for loading a packed floating-point operand into a register file entry having one or more associated implicit bits. The packed floating point operand includes multiple component operands. Significand and exponent bits for each component operand are copied to corresponding fields of the register entry, and the exponent bits are tested to determine whether the component operand is normalized. An implicit bit corresponding to the component operand is set when the component operand is normalized.
摘要翻译： 提供了一种用于将打包的浮点操作数加载到具有一个或多个相关隐含位的寄存器文件条目中的方法。 打包浮点操作数包括多个组件操作数。 每个组件操作数的有效位和指数位被复制到寄存器条目的相应字段，并且测试指数位以确定组件操作数是否被归一化。 当组件操作数被归一化时，设置与组件操作数相对应的隐式位。
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公开(公告)号：US20110055469A1
公开(公告)日：2011-03-03
申请号：US12550737
申请日：2009-08-31
申请人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G06F12/06
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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6.发明授权公开(公告)号：US06370639B1
公开(公告)日：2002-04-09
申请号：US09169482
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi , Guillermo Juan Rozas
IPC分类号： G06F9312
CPC分类号： G06F9/3865 , G06F9/30014 , G06F9/30094 , G06F9/3842
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。
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7.发明授权公开(公告)号：US08593960B2
公开(公告)日：2013-11-26
申请号：US12827495
申请日：2010-06-30
申请人： Michael Kauschke , Gautam B. Doshi
发明人： Michael Kauschke , Gautam B. Doshi
CPC分类号： H04L47/826 , H04L45/06 , H04L47/50 , H04L49/00 , H04L49/109 , H04L49/1584 , H04L49/3063 , H04L49/90
摘要： In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于确定在节点的输入/输出（I / O）电路中接收的分组是否发往该节点的方法，如果是，则将分组提供给I / O电路并且确定I / O电路的入口队列中是否存在一个或多个分组，并且如果是，则根据与业务流独立的全局调度将选择的分组提供给第一或第二输出寄存器。 描述和要求保护其他实施例。
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8.发明授权Enabling storage of active state in internal storage of processor rather than in SMRAM upon entry to system management mode 有权在进入系统管理模式时，将活动状态存储在处理器的内部存储器中，而不是在SMRAM中公开(公告)号：US08578138B2
公开(公告)日：2013-11-05
申请号：US12550737
申请日：2009-08-31
申请人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
发明人： Mahesh S. Natu , Thanunathan Rangarajan , Gautam B. Doshi , Shammanna M. Datta , Baskaran Ganesan , Mohan J. Kumar , Rajesh S. Parthasarathy , Frank Binns , Rajesh Nagaraja Murthy , Robert C. Swanson
IPC分类号： G06F9/48
CPC分类号： G06F13/24 , G06F9/30101 , G06F9/3017 , G06F9/30189 , G06F9/3851 , G06F9/461 , G11C7/1072 , G11C11/40615
摘要： In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有诸如静态随机存取存储器之类的片上存储器的处理器，用于存储在进入系统时从处理器的架构状态存储器交换的一个或多个线程的架构状态 管理模式（SMM）。 以这种方式，可以避免该状态信息与系统管理存储器的通信，减少与进入SMM相关联的延迟。 实施例还可以使处理器更新处于长指令流或处于系统管理中断（SMI）阻塞状态中的执行代理的状态，以向SMM内的代理提供指示。 描述和要求保护其他实施例。
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9.发明申请PROVIDING A BUFFERLESS TRANSPORT METHOD FOR MULTI-DIMENSIONAL MESH TOPOLOGY 审中-公开提供一种用于多维网格拓扑的无缓冲传输方法公开(公告)号：US20140050224A1
公开(公告)日：2014-02-20
申请号：US14063858
申请日：2013-10-25
申请人： Michael Kauschke , Gautam B. Doshi
发明人： Michael Kauschke , Gautam B. Doshi
IPC分类号： H04L12/911 , H04L12/863
CPC分类号： H04L47/826 , H04L45/06 , H04L47/50 , H04L49/00 , H04L49/109 , H04L49/1584 , H04L49/3063 , H04L49/90
摘要： In one embodiment, the present invention includes a method for determining whether a packet received in an input/output (I/O) circuit of a node is destined for the node and if so, providing the packet to an egress queue of the I/O circuit and determining whether one or more packets are present in an ingress queue of the I/O circuit and if so, providing a selected packet to a first or second output register according to a global schedule that is independent of traffic flow. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于确定在节点的输入/输出（I / O）电路中接收的分组是否发往该节点的方法，如果是，则将分组提供给I / O电路并且确定I / O电路的入口队列中是否存在一个或多个分组，并且如果是，则根据与业务流独立的全局调度将选择的分组提供给第一或第二输出寄存器。 描述和要求保护其他实施例。
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10.发明授权Methods and apparatus for handling and storing bi-endian words in a floating-point processor 有权用于在浮点处理器中处理和存储双向字的方法和装置公开(公告)号：US06212539B1
公开(公告)日：2001-04-03
申请号：US09169483
申请日：1998-10-10
申请人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
发明人： Jerome C. Huck , Peter Markstein , Glenn T. Colon-Bonet , Alan H. Karp , Roger Golliver , Michael Morrison , Gautam B. Doshi
IPC分类号： G06F700
摘要： A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.
摘要翻译： 计算机的浮点单元包括浮点计算单元，浮点寄存器和浮点状态寄存器。 浮点状态寄存器可以包括主状态字段和一个或多个备用状态字段。 每个状态字段都包含标志和控制信息。 不同的浮点运算可能与不同的状态字段相关联。 浮点状态寄存器的子字段可以在操作期间动态更新。 替代状态字段的控制位可以包括用于在推测执行期间推迟中断的陷阱禁止位。 当中间结果的指数在寄存器格式的范围内但超出存储器格式的范围时，可以使用状态字段中的最大范围指数控制位来防止中断。 浮点数据可以以大端或小端格式存储。
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