发明授权
US07037845B2 Selective etch process for making a semiconductor device having a high-k gate dielectric
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用于制造具有高k栅极电介质的半导体器件的选择性蚀刻工艺
- 专利标题： Selective etch process for making a semiconductor device having a high-k gate dielectric
- 专利标题（中）： 用于制造具有高k栅极电介质的半导体器件的选择性蚀刻工艺
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申请号： US10652546申请日： 2003-08-28
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公开(公告)号： US07037845B2公开(公告)日： 2006-05-02
- 发明人: Justin K. Brask , Uday Shah , Mark L. Doczy , Jack Kavalieros , Robert S. Chau , Robert B. Turkot, Jr. , Matthew V. Metz
- 申请人： Justin K. Brask , Uday Shah , Mark L. Doczy , Jack Kavalieros , Robert S. Chau , Robert B. Turkot, Jr. , Matthew V. Metz
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： H01L21/302
- IPC分类号： H01L21/302
摘要：
A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, and modifying a first portion of the high-k gate dielectric layer to ensure that it may be removed selectively to a second portion of the high-k gate dielectric layer.
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