发明授权
- 专利标题: Method for forming a metal interconnection layer of a semiconductor device using a modified dual damascene process
- 专利标题(中): 使用改进的双镶嵌工艺形成半导体器件的金属互连层的方法
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申请号: US10449973申请日: 2003-05-30
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公开(公告)号: US07041592B2公开(公告)日: 2006-05-09
- 发明人: Jae-hak Kim , Soo-geun Lee , Kyung-woo Lee
- 申请人: Jae-hak Kim , Soo-geun Lee , Kyung-woo Lee
- 申请人地址: KR Suwon
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon
- 代理机构: F. Chau & Associates, LLC
- 优先权: KR10-2002-0045610 20020801
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
A method for forming a metal interconnection layer of a semiconductor device comprises forming a film including a material selective to a medium used in an ashing process on an interlayer insulating film. The method comprises transforming the film during the ashing process to form an interconnection pattern having a dual damascene structure. A dielectric material such as copper is deposited on the interconnection pattern, which is planarized through CMP, thereby forming a via contact having a single damascene structure without a recess therein.
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