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    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method
    2.
    发明授权
    Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method 有权
    形成半导体器件的金属互连的方法以及通过这种方法形成的金属互连

    公开(公告)号：US07446033B2

    公开(公告)日：2008-11-04

    申请号：US11336905

    申请日：2006-01-23

    申请人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    发明人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

    IPC分类号： H01L21/4763 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76883 ,  Y10T428/24207

    摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

    摘要翻译： 使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。 首先，在层间电介质层的开口中依次形成阻挡层和金属层。 在金属层上进行CMP工艺以形成残留在开口内的金属互连。 然后，用等离子体处理金属互连。 等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。 此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。 然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。 最后，形成封盖绝缘层。 通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

    Structure of a CMOS image sensor and method for fabricating the same
    3.
    发明授权
    Structure of a CMOS image sensor and method for fabricating the same 有权
    CMOS图像传感器的结构及其制造方法

    公开(公告)号：US07400003B2

    公开(公告)日：2008-07-15

    申请号：US10998803

    申请日：2004-11-30

    申请人： Soo-Geun Lee ,  Ki-Chul Park ,  Kyoung-Woo Lee

    发明人： Soo-Geun Lee ,  Ki-Chul Park ,  Kyoung-Woo Lee

    IPC分类号： H01L31/062

    CPC分类号： H01L23/53238 ,  G01R31/2829 ,  H01L21/76805 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687 ,  H01L31/022408 ,  H01L2924/0002 ,  H04N17/002 ,  H01L2924/00

    摘要： An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

    摘要翻译： 图像传感器装置及其形成方法包括形成在基板中的光电二极管，与光电二极管电连接的至少一个电互连线，具有光入口的光通路，光通路与光电二极管对准， 位于光通道的光入口之上的滤色器和位于滤光器上的透镜与光通路对准，其中至少一个电互连线包括铜互连结构，铜互连结构具有层叠形式的多个层间电介质层， 相邻的层间电介质层之间的扩散阻挡层和铜互连结构与多个层间电介质层之间的阻挡金属层以及介于其间的扩散阻挡层。 如果从光电二极管上方去除阻挡金属层，则图像传感器装置可以采用铜互连。

    Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the same
    4.
    发明授权
    Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the same 失效
    金属绝缘体 - 金属电容器的双镶嵌互连及其制造方法

    公开(公告)号：US07279733B2

    公开(公告)日：2007-10-09

    申请号：US10799292

    申请日：2004-03-12

    申请人： Kyoung-woo Lee ,  Soo-geun Lee

    发明人： Kyoung-woo Lee ,  Soo-geun Lee

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L21/76807 ,  H01L23/5223 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided are a dual damascene interconnection with a metal-insulator-metal (MIM) capacitor and a method of fabricating the same. In this structure, an MIM capacitor is formed on a via-level IMD. After the via-level IMD is formed, while an alignment key used for patterning the MIM capacitor is being formed, a via hole is formed to connect a lower electrode of the MIM capacitor and an interconnection disposed under the via-level IMD. Also, an upper electrode of the MIM capacitor is directly connected to an upper metal interconnection during a dual damascene process.

    摘要翻译： 提供了一种与金属 - 绝缘体 - 金属（MIM）电容器的双镶嵌互连及其制造方法。 在该结构中，在通孔级IMD上形成MIM电容器。 在形成通孔级IMD之后，当形成MIM电容器图形化的对准键时，形成通孔，以连接MIM电容器的下电极和配置在通孔级IMD下的互连。 此外，在双镶嵌工艺期间，MIM电容器的上电极直接连接到上金属互连。

    Inter-metal dielectric patterns and method of forming the same
    9.
    发明授权
    Inter-metal dielectric patterns and method of forming the same 失效
    金属间电介质图案及其形成方法

    公开(公告)号：US06849536B2

    公开(公告)日：2005-02-01

    申请号：US10404210

    申请日：2003-04-01

    申请人： Soo-Geun Lee ,  Ju-Hyuk Chung ,  Il-Goo Kim ,  Kyoung-Woo Lee ,  Wan-Jae Park ,  Jae-Hak Kim

    发明人： Soo-Geun Lee ,  Ju-Hyuk Chung ,  Il-Goo Kim ,  Kyoung-Woo Lee ,  Wan-Jae Park ,  Jae-Hak Kim

    IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4762

    CPC分类号： H01L21/76831 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76835 ,  H01L2221/1036

    摘要： Provided are an inter-metal dielectric pattern and a method of forming the same. The pattern includes a lower interconnection disposed on a semiconductor substrate, a lower dielectric layer having a via hole exposing the lower interconnection and covering the semiconductor substrate where the lower interconnection is disposed, and an upper dielectric pattern and a lower capping pattern, which include a trench line exposing the via hole and sequentially stacked on the lower dielectric layer. The lower dielectric layer and the upper dielectric pattern are low k-dielectric layers formed of materials such as SiO2, SiOF, SiOC, and porous dielectric. The method includes forming an inter-metal dielectric layer including a lower dielectric layer and upper dielectric layer, which are sequentially stacked, on a lower interconnection formed on a semiconductor substrate. The inter-metal dielectric layer is patterned to form a via hole, which exposes the upper side of the lower interconnection. Then, an upper capping layer is formed on the entire surface of the semiconductor substrate including the via hole. The upper capping layer and the upper dielectric layer are successively patterned to form a trench line exposing the upper side of the via hole. The upper capping layer is formed of at least one material selected from the group consisting of a silicon oxide layer, a silicon carbide layer, a silicon nitride layer, and a silicon oxynitride layer, by using PECVD.

    摘要翻译： 提供了金属间介电图案及其形成方法。 该图案包括布置在半导体衬底上的下部互连，具有通孔暴露下部互连并覆盖半导体衬底的下部电介质图案和下部封盖图案的下部电介质层， 沟槽线暴露通孔并依次堆叠在下介电层上。 下电介质层和上电介质图案是由诸如SiO 2，SiOF，SiOC和多孔电介质的材料形成的低K电介质层。 该方法包括在形成在半导体衬底上的下互连件上依次层叠包括下电介质层和上电介质层的金属间电介质层。 图案化金属间电介质层以形成通孔，其暴露下部互连的上侧。 然后，在包括通孔的半导体衬底的整个表面上形成上覆盖层。 上覆盖层和上电介质层被连续地图案化以形成暴露通孔上侧的沟槽线。 通过使用PECVD，上覆盖层由选自氧化硅层，碳化硅层，氮化硅层和氮氧化硅层的至少一种材料形成。

    Integrated circuit capacitor structure
    10.
    发明授权
    Integrated circuit capacitor structure 失效
    集成电路电容器结构

    公开(公告)号：US07560332B2

    公开(公告)日：2009-07-14

    申请号：US11733711

    申请日：2007-04-10

    申请人： Kyoung-Woo Lee ,  Wan-Jae Park ,  Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Mu-Kyeng Jung ,  Yong-Jun Lee ,  Il-Goo Kim ,  Soo-Geun Lee

    发明人： Kyoung-Woo Lee ,  Wan-Jae Park ,  Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Mu-Kyeng Jung ,  Yong-Jun Lee ,  Il-Goo Kim ,  Soo-Geun Lee

    IPC分类号： H01L21/8234

    CPC分类号： H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

    摘要翻译： 本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。