发明授权
- 专利标题： Method for forming bit line
- 专利标题（中）： 位线形成方法
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申请号： US10459327申请日： 2003-06-11
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公开(公告)号： US07052949B2公开(公告)日： 2006-05-30
- 发明人: Kuo-Chien Wu , Tse-Yao Huang , Yi-Nan Chen
- 申请人： Kuo-Chien Wu , Tse-Yao Huang , Yi-Nan Chen
- 申请人地址： TW Taoyuan
- 专利权人： Nanya Technology Corporation
- 当前专利权人： Nanya Technology Corporation
- 当前专利权人地址： TW Taoyuan
- 代理机构： Quintero Law Office
- 优先权： TW91138102A 20021231
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763 ; H01L21/8238
摘要：
A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.
公开/授权文献
- US20040127013A1 Method for forming bit line 公开/授权日：2004-07-01
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