公开(公告)号：US07807558B2

公开(公告)日：2010-10-05

申请号：US11933732

申请日：2007-11-01

申请人： Tzu-Ching Tsai ,  Tse-Yao Huang ,  Yi-Nan Chen

发明人： Tzu-Ching Tsai ,  Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/02063 ,  H01L21/02071 ,  H01L21/32137

摘要： A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device comprises providing a substrate. Next, an insulating layer, a conductive layer and a silicide layer are formed on the substrate in sequence. Next, a hard masking layer is formed on the silicide layer exposing a portion of the silicide layer. A first etching step is performed to remove the silicide layer and the underlying conductive layer which are not covered by the hard masking layer, thereby forming a gate stack. And next, a second etching step is performed to remove any remaining conductive layer not covered by the hard masking layer after the first etching step. The second etching step is performed with an etchant comprising ammonium hydroxide.

摘要翻译： 提供一种制造半导体器件的方法。 制造半导体器件的方法包括提供衬底。 接下来，依次在基板上形成绝缘层，导电层和硅化物层。 接下来，在暴露硅化物层的一部分的硅化物层上形成硬掩模层。 执行第一蚀刻步骤以去除未被硬掩模层覆盖的硅化物层和下面的导电层，从而形成栅极堆叠。 接下来，执行第二蚀刻步骤以在第一蚀刻步骤之后去除未被硬掩模层覆盖的剩余导电层。 用包含氢氧化铵的蚀刻剂进行第二蚀刻步骤。

公开(公告)号：US07696108B2

公开(公告)日：2010-04-13

申请号：US11953072

申请日：2007-12-09

申请人： Wen-Chieh Wang ,  Jin-Tau Huang ,  Wei-Hui Hsu ,  Tse-Yao Huang

发明人： Wen-Chieh Wang ,  Jin-Tau Huang ,  Wei-Hui Hsu ,  Tse-Yao Huang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/32

摘要： A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.

摘要翻译： 提供了一种在晶片斜面区域上形成阴影层的方法。 首先，提供具有晶片斜面区域和中心区域的基板。 此后，设置上绝缘体和下绝缘体。 上绝缘体设置在基板的上表面上，并且至少覆盖中心区域。 下绝缘体设置在基板的下表面上，并且至少覆盖中心区域。 然后，在未被上绝缘体覆盖的上表面上和未被下绝缘体覆盖的下表面上形成阴影层。 接下来，去除上绝缘体和下绝缘体。

公开(公告)号：US07094638B2

公开(公告)日：2006-08-22

申请号：US10605678

申请日：2003-10-17

申请人： Jin-Tau Huang ,  Chung-Peng Hao ,  Yi-Nan Chen ,  Tse-Yao Huang

发明人： Jin-Tau Huang ,  Chung-Peng Hao ,  Yi-Nan Chen ,  Tse-Yao Huang

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L21/28247 ,  H01L21/28061

摘要： A method of forming a gate structure. First, a substrate is provided, and a gate oxide layer, a polysilicon layer, a silicide layer, and a cap layer are consecutively formed onto the substrate. Then, an etching process is performed to etch a portion of the cap layer, the silicide layer, and the polysilicon layer and stop on the polysilicon layer for forming a stacked gate. Thereafter, a portion of the silicide layer exposed on sidewalls of the stacked gate is removed to form a recess. A passivation layer is deposited to fill the recess. The remaining polysilicon layer and the gate oxide layer outside the sidewalls of the stacked gate structure are removed.

摘要翻译： 一种形成栅极结构的方法。 首先，提供基板，并且在基板上连续地形成栅氧化层，多晶硅层，硅化物层和盖层。 然后，进行蚀刻处理以蚀刻覆盖层，硅化物层和多晶硅层的一部分，并停留在多晶硅层上以形成堆叠栅极。 此后，去除暴露在堆叠栅极的侧壁上的硅化物层的一部分以形成凹陷。 沉积钝化层以填充凹部。 除去堆叠栅结构的侧壁外的剩余多晶硅层和栅氧化层。

公开(公告)号：US07052949B2

公开(公告)日：2006-05-30

申请号：US10459327

申请日：2003-06-11

申请人： Kuo-Chien Wu ,  Tse-Yao Huang ,  Yi-Nan Chen

发明人： Kuo-Chien Wu ,  Tse-Yao Huang ,  Yi-Nan Chen

IPC分类号： H01L21/4763 ,  H01L21/8238

CPC分类号： H01L21/76802 ,  H01L27/10888 ,  H01L27/10894

摘要： A method for forming a bit line. A semiconductor substrate is provided. A MOS having a gate and an S/D area is formed on the semiconductor substrate. A first dielectric layer with a first opening is formed on the semiconductor substrate to expose the S/D area. A conducting layer is formed in the first opening. A barrier layer is formed on the surface of the first dielectric layer and the conducting layer. A second dielectric layer having a second opening and a third opening is formed on the barrier layer, the position of the second opening corresponding to the first opening. Metal layers are formed in the second opening and the third opening as bit lines, respectively.

摘要翻译： 一种形成位线的方法。 提供半导体衬底。 在半导体衬底上形成具有栅极和S / D区域的MOS。 在半导体衬底上形成具有第一开口的第一电介质层，以暴露S / D区域。 在第一开口中形成导电层。 在第一电介质层和导电层的表面上形成阻挡层。 具有第二开口和第三开口的第二电介质层形成在阻挡层上，第二开口的位置对应于第一开口。 分别在第二开口和第三开口中形成金属层作为位线。

公开(公告)号：US20050277258A1

公开(公告)日：2005-12-15

申请号：US10940707

申请日：2004-09-15

申请人： Tse-Yao Huang ,  Kuo-Chien Wu ,  Yi-Nan Chen

发明人： Tse-Yao Huang ,  Kuo-Chien Wu ,  Yi-Nan Chen

IPC分类号： H01L21/02 ,  H01L21/60 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/105

CPC分类号： H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L21/823871 ,  H01L27/105 ,  H01L27/1052

摘要： A method for forming a self-aligned contact on a semiconductor substrate provided with a plurality of field-effect transistors. The method comprises the steps of: forming a thin nitride insulating layer on a gate structure and a diffusion region of the transistor; forming a first insulating layer, which is then planarized to expose the nitride insulating layer on the gate structure; etching through the first insulating layer to form a first part of a contact hole; forming a first part of a contact in said first part of the contact hole; forming a second insulating layer; etching through the second insulating layer to form a second part of the contact hole; and forming a second part of the contact in the second part of the contact hole. The two-stage etching process for forming a conductive contact effectively prevents over-etching and short-circuiting between a wordline and a bitline.

摘要翻译： 一种用于在设置有多个场效应晶体管的半导体衬底上形成自对准接触的方法。 该方法包括以下步骤：在晶体管的栅极结构和扩散区上形成薄的氮化物绝缘层; 形成第一绝缘层，然后将其平坦化以暴露栅极结构上的氮化物绝缘层; 蚀刻穿过第一绝缘层以形成接触孔的第一部分; 在所述接触孔的所述第一部分中形成接触的第一部分; 形成第二绝缘层; 蚀刻穿过第二绝缘层以形成接触孔的第二部分; 以及在接触孔的第二部分中形成接触的第二部分。 用于形成导电接触的两级蚀刻工艺有效地防止了字线和位线之间的过蚀刻和短路。

公开(公告)号：US20050106887A1

公开(公告)日：2005-05-19

申请号：US10783467

申请日：2004-02-20

申请人： Yi-Nan Chen ,  Tse-Yao Huang ,  Hui-Min Mao

发明人： Yi-Nan Chen ,  Tse-Yao Huang ,  Hui-Min Mao

IPC分类号： H01L21/28 ,  H01L21/283 ,  H01L21/302 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76897

摘要： A method of forming contact holes. A substrate on which a plurality of gate structures is formed is provided, wherein the gate structure comprises a gate, a gate capping layer, and a gate spacer. An insulating layer is formed on the gate structures and fills between the gate structures. The insulating layer is etched using the gate capping layers, the gate spacers, and the substrate as stop layers to form first contact holes between the gate structures to expose the substrate and the gate spacers and form second contact holes overlying each gate structure to expose the gate capping layers. A protective spacer is formed over each sidewall of the first contact holes and the second contact holes. The gate capping layer under each gate contact hole is etched using the protective spacer as a stop layer to expose the gate. The protective spacers are removed.

摘要翻译： 一种形成接触孔的方法。 提供形成有多个栅极结构的基板，其中栅极结构包括栅极，栅极覆盖层和栅极间隔物。 在栅极结构上形成绝缘层，并填充在栅极结构之间。 使用栅极覆盖层，栅极间隔物和衬底作为停止层来蚀刻绝缘层，以在栅极结构之间形成第一接触孔，以暴露衬底和栅极间隔物，并形成覆盖每个栅极结构的第二接触孔，以暴露出 门盖层。 在第一接触孔和第二接触孔的每个侧壁上形成保护隔离物。 在每个栅极接触孔下方的栅极覆盖层使用保护隔板作为停止层进行蚀刻，以露出栅极。 去除保护性间隔物。

公开(公告)号：US20050054206A1

公开(公告)日：2005-03-10

申请号：US10653882

申请日：2003-09-04

申请人： Tse-Yao Huang ,  Chang-Ming Wu

发明人： Tse-Yao Huang ,  Chang-Ming Wu

IPC分类号： H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768

CPC分类号： H01L21/31116 ,  H01L21/76802

摘要： Disclosed is an etching method for forming a high aspect ratio contact hole. The plasma gas composition for the etching comprises Ar, a first fluorocarbon, O2 and a second fluorocarbon, wherein the fluorine-to-carbon ratio of the second fluorocarbon is higher than that of the first fluorocarbon. The method of the present invention can maintain the profile of the contact hole well, and reduce the accumulation of the etch stop generated during etching.

摘要翻译： 公开了用于形成高纵横比接触孔的蚀刻方法。 用于蚀刻的等离子体气体组合物包括Ar，第一碳氟化合物O 2和第二碳氟化合物，其中第二碳氟化合物的氟碳比高于第一碳氟化合物。 本发明的方法可以良好地保持接触孔的轮廓，并且减少蚀刻期间产生的蚀刻停止的累积。

公开(公告)号：US06767837B2

公开(公告)日：2004-07-27

申请号：US10379969

申请日：2003-03-05

申请人： Yu-Chi Sun ,  Tse-Yao Huang

发明人： Yu-Chi Sun ,  Tse-Yao Huang

IPC分类号： H01L21302

CPC分类号： H01L21/31116 ,  H01L21/31055

摘要： A method of inter-layer dielectric (ILD) or inter-metal dielectric (IMD) planarization. Reactive ion etching (RIE) is performed with gases including equal amounts of C5F8 and CHF3, and argon diluent gas. The ratio of the gas is precisely controlled in the etching, and once the oxygen concentration drops, the etching process enters deposition of the protection layer, and when oxygen concentration drops to a minimum level, the etch-back process stops automatically. Higher ILD or IMD uniformity is achieved compared with conventional CMP process.

公开(公告)号：US06759300B2

公开(公告)日：2004-07-06

申请号：US10424526

申请日：2003-04-28

申请人： Chao-Wen Lay ,  Yu-Chi Sun ,  Tse-Yao Huang

发明人： Chao-Wen Lay ,  Yu-Chi Sun ,  Tse-Yao Huang

IPC分类号： H01L218247

CPC分类号： H01L21/28273 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/42324

摘要： A method for fabricating a floating gate. A semiconductor substrate is provided, on which a gate dielectric layer, a conductive layer, a first insulating layer, and a patterned mask layer with an opening are formed, such that the opening exposes the first insulating layer. The insulating layer and the conducting layer are sequentially etched to form a round-cornered trench, and the photo hard mask layer is removed. A second insulating layer is formed in the round-cornered trench. The first insulating layer and the exposed conducting layer are removed using the second insulating layer as a mask, and the first conducting layer covered by the second insulating layer remains as a floating gate.

摘要翻译： 一种用于制造浮动栅极的方法。 提供半导体衬底，其上形成有栅极电介质层，导电层，第一绝缘层和具有开口的图案化掩模层，使得开口暴露第一绝缘层。 依次蚀刻绝缘层和导电层以形成圆角沟槽，并去除光硬掩模层。 在圆角沟槽中形成第二绝缘层。 使用第二绝缘层作为掩模去除第一绝缘层和暴露的导电层，并且由第二绝缘层覆盖的第一导电层保持为浮栅。

公开(公告)号：US06140179A

公开(公告)日：2000-10-31

申请号：US326651

申请日：1999-06-07

申请人： Yinan Chen ,  Shih-chi Hsu ,  Tse Yao Huang

发明人： Yinan Chen ,  Shih-chi Hsu ,  Tse Yao Huang

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L21/8242

CPC分类号： H01L28/82 ,  H01L27/10814 ,  H01L28/87 ,  H01L28/91

摘要： The present invention discloses a method of forming a crown capacitor for a DRAM cell. An etching method having different selectivity between the BPSG and silicon oxynitride layer is applied to form a sacrificial structure with a concanovenex sidewall. Using the sacrificial structure as a mold, a high capacitance crown capacitor is obtained.

摘要翻译： 本发明公开了一种形成用于DRAM单元的表冠电容器的方法。 施加在BPSG和氮氧化硅层之间具有不同选择性的蚀刻方法以形成具有锥形侧壁的牺牲结构。 使用牺牲结构作为模具，获得高电容冠电容器。