Method for forming wire line by damascene process using hard mask formed from contacts

Invention Grant

US07052952B2 Method for forming wire line by damascene process using hard mask formed from contacts 失效

Title translation: 通过使用由接触形成的硬掩模的镶嵌工艺形成金属丝线的方法

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Patent Title: Method for forming wire line by damascene process using hard mask formed from contacts
Patent Title (中): 通过使用由接触形成的硬掩模的镶嵌工艺形成金属丝线的方法
Application No.: US10779494

Application Date: 2004-02-13
Publication No.: US07052952B2

Publication Date: 2006-05-30
Inventor: In-deog Bae , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi
Applicant: In-deog Bae , Chang-jin Kang , Jeong-sic Jeon , Kyeong-koo Chi
Applicant Address: KR Suwon-si
Assignee: Samsung Electronics Co., Ltd
Current Assignee: Samsung Electronics Co., Ltd
Current Assignee Address: KR Suwon-si
Agency: F. Chau & Associates, LLC
Priority: KR10-2003-0009359 20030214
Main IPC: H01L21/8242
IPC: H01L21/8242

Method for forming wire line by damascene process using hard mask formed from contacts

Abstract:

A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

Abstract(Chinese):

通过镶嵌工艺形成导线的方法包括在半导体衬底上形成第一绝缘层，蚀刻第一绝缘层以形成接触孔，并在填充接触孔的第一绝缘层上形成第一导电层。图案化第一导电层，并且形成填充接触孔并与半导体衬底电连接的存储节点接触。在存储节点接触件上形成硬掩模，并且使用硬掩模作为蚀刻掩模蚀刻第一绝缘层，以在第一绝缘层中形成沟槽。在与半导体衬底电连接的沟槽中形成位线。形成覆盖位线的第二绝缘层。第二绝缘层和硬掩模被平坦化，并且在存储节点接触件上形成电容器的存储节点。

Public/Granted literature

US20040161923A1 Method for forming wire line by damascene process using hard mask formed from contacts Public/Granted day:2004-08-19

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8239	........存储器结构
H01L21/8242	.........动态随机存取存储结构（DRAM）