公开(公告)号：US07052952B2

公开(公告)日：2006-05-30

申请号：US10779494

申请日：2004-02-13

申请人： In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

发明人： In-deog Bae ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi

IPC分类号： H01L21/8242

CPC分类号： H01L27/10885 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/0214 ,  H01L27/10855 ,  Y10S438/978

摘要： A method for forming a wire line by a damascene process includes forming a first insulating layer on a semiconductor substrate, etching the first insulating layer to form a contact hole, and forming a first conductive layer over the first insulating layer that fills the contact hole. The first conductive layer is patterned, and a storage node contact is formed that fills the contact hole and is electrically connected to the semiconductor substrate. A hard mask is formed over the storage node contact and the first insulating layer is etched using the hard mask as an etch mask to form a trench in the first insulating layer. A bit line is formed in the trench that is electrically connected to the semiconductor substrate. A second insulating layer is formed that covers the bit line. The second insulating layer and the hard mask are planarized and a storage node of a capacitor is formed on the storage node contact.

摘要翻译： 通过镶嵌工艺形成导线的方法包括在半导体衬底上形成第一绝缘层，蚀刻第一绝缘层以形成接触孔，并在填充接触孔的第一绝缘层上形成第一导电层。 图案化第一导电层，并且形成填充接触孔并与半导体衬底电连接的存储节点接触。 在存储节点接触件上形成硬掩模，并且使用硬掩模作为蚀刻掩模蚀刻第一绝缘层，以在第一绝缘层中形成沟槽。 在与半导体衬底电连接的沟槽中形成位线。 形成覆盖位线的第二绝缘层。 第二绝缘层和硬掩模被平坦化，并且在存储节点接触件上形成电容器的存储节点。

公开(公告)号：US20060284277A1

公开(公告)日：2006-12-21

申请号：US11510349

申请日：2006-08-25

申请人： Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

发明人： Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

IPC分类号： H01L29/00

CPC分类号： H01L27/10885 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/10888 ,  H01L27/10891

摘要： A semiconductor device includes an insulating layer having a T-shaped groove formed by a wide opening overlapping a narrow opening, a bit line conductive layer that at least partially fills the narrow opening, and a bit line capping layer that fills the groove so that its top surface is as high as that of the insulating layer. Spacers are formed on the inner walls of the wide opening.

摘要翻译： 半导体器件包括：绝缘层，其具有由窄开口重叠的宽开口形成的T形槽，至少部分填充窄开口的位线导电层和填充槽的位线封盖层，使得其 顶表面与绝缘层一样高。 隔板形成在宽开口的内壁上。

公开(公告)号：US06607954B2

公开(公告)日：2003-08-19

申请号：US10304273

申请日：2002-11-26

申请人： Jeong-sic Jeon ,  Kyeong-koo Chi ,  Chang-jin Kang ,  Jin-hwan Hahm

发明人： Jeong-sic Jeon ,  Kyeong-koo Chi ,  Chang-jin Kang ,  Jin-hwan Hahm

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

摘要： A capacitor for a semiconductor memory device is fabricated by forming a mold layer on a semiconductor substrate that includes a peripheral circuit area and a cell array area which includes a plug in a buried contact hole. A hard mask layer pattern is formed on the mold layer. The mold layer is etched, using the hard mask layer pattern as an etch mask, to form a mold layer pattern. The hard mask layer pattern is then removed from the mold layer pattern or only partially etched back on the mold layer pattern. A capacitor lower electrode is formed along the walls of the buried contact hole and on a surface of the mold layer pattern. A capacitor dielectric layer is formed on the capacitor lower electrode and a capacitor upper electrode is formed on the capacitor dielectric layer.

摘要翻译： 半导体存储器件的电容器是通过在包括外围电路区域的半导体衬底上形成模层而形成的，以及包括埋入接触孔中的插头的单元阵列区域。 在模具层上形成硬掩模层图案。 使用硬掩模层图案作为蚀刻掩模蚀刻模具层以形成模具层图案。 然后将硬掩模层图案从模具层图案中移除，或者仅在模具层图案上部分地蚀刻回去。 电容器下电极沿掩埋接触孔的壁和模层图案的表面形成。 在电容器下电极上形成电容器电介质层，在电容器电介质层上形成电容器上电极。

公开(公告)号：US07098135B2

公开(公告)日：2006-08-29

申请号：US10703328

申请日：2003-11-07

申请人： Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

发明人： Seung-pil Chung ,  Chang-jin Kang ,  Jeong-sic Jeon ,  Kyeong-koo Chi ,  Seung-young Son ,  Sang-yong Kim

IPC分类号： H01L21/311

CPC分类号： H01L27/10885 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/10888 ,  H01L27/10891

摘要： A semiconductor device including a bit line formed using a damascene technique and a method of fabricating the same. The method includes forming an insulating layer on a substrate, forming a groove by etching the insulating layer to a partial depth, and forming spacers on the inner walls of the groove. An opening is formed by etching the insulating layer disposed under the groove using the spacers as an etch mask. A conductive layer is formed to fill the opening. A capping layer is formed to fill the groove.

摘要翻译： 一种包括使用镶嵌技术形成的位线的半导体器件及其制造方法。 该方法包括在基板上形成绝缘层，通过将绝缘层蚀刻到局部深度形成沟槽，并在槽的内壁上形成间隔物。 通过使用间隔物作为蚀刻掩模蚀刻设置在凹槽下方的绝缘层来形成开口。 形成导电层以填充开口。 形成覆盖层以填充凹槽。

公开(公告)号：US20060246666A1

公开(公告)日：2006-11-02

申请号：US11410837

申请日：2006-04-26

申请人： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

发明人： Jeong-nam Han ,  Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi ,  Woo-gwan Shim ,  Hyo-san Lee ,  Chang-ki Hong ,  Sang-jun Choi

IPC分类号： H01L21/336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11543

摘要： A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.

摘要翻译： 提供一种制造具有U形浮动栅极的闪速存储器的方法。 该方法包括形成由间隙隔开并在间隙中形成隧道氧化物层的相邻隔离层。 在隧道氧化物层上形成导电层至不填充间隙的厚度之后，在导电层上形成抛光牺牲层。 除去隔离层上的牺牲层和导电层，从而在间隙中形成自对准的U形浮动栅极，同时在浮栅的内部部分内形成牺牲层图案。 然后将选定的隔离层凹入以露出浮动栅极的侧壁。 然后从浮动栅极去除牺牲层图案以暴露浮动栅极的上表面。

公开(公告)号：US07709389B2

公开(公告)日：2010-05-04

申请号：US11480545

申请日：2006-07-05

申请人： Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi

发明人： Dong-chan Kim ,  Chang-jin Kang ,  Kyeong-koo Chi

IPC分类号： H01L21/302

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/76816 ,  H01L21/76897 ,  Y10S438/947

摘要： A method of fabricating a semiconductor device comprising a method of forming an etching mask used for etching a semiconductor base material is disclosed. The method of fabricating a semiconductor device comprises forming hard mask patterns on a semiconductor base material; forming material layers covering the lateral and top surfaces of the hard mask patterns to form openings between adjacent hard mask patterns, wherein the width of each opening is smaller than the distance between adjacent hard mask patterns; and etching the semiconductor base material using the hard mask patterns and material layers as an etching mask.

摘要翻译： 公开了一种制造半导体器件的方法，包括形成用于蚀刻半导体基底材料的蚀刻掩模的方法。 制造半导体器件的方法包括在半导体基底材料上形成硬掩模图案; 形成覆盖硬掩模图案的侧表面和顶表面的材料层，以在相邻的硬掩模图案之间形成开口，其中每个开口的宽度小于相邻硬掩模图案之间的距离; 并使用硬掩模图案和材料层作为蚀刻掩模蚀刻半导体基底材料。

公开(公告)号：US20050287738A1

公开(公告)日：2005-12-29

申请号：US11159130

申请日：2005-06-23

申请人： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

发明人： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L27/10852 ,  H01L28/91

摘要： A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

摘要翻译： 半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案， 蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层， 所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

公开(公告)号：US07402488B2

公开(公告)日：2008-07-22

申请号：US11159130

申请日：2005-06-23

申请人： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

发明人： Sung-il Cho ,  Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Cheol-kyu Lee

IPC分类号： H01L21/8242

CPC分类号： H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L27/10852 ,  H01L28/91

摘要： A method of manufacturing a semiconductor memory device includes forming a carbon-containing layer on a semiconductor substrate, forming an insulating layer pattern on the carbon-containing layer, the insulating layer pattern partially exposing an upper surface of the carbon-containing layer, dry-etching the exposed portion of the carbon-containing layer, to form a carbon-containing layer pattern for defining a storage node hole, forming a bottom electrode inside the storage node hole, forming a dielectric layer on the bottom electrode inside the storage node hole, the dielectric layer covering the bottom electrode, and forming an upper electrode on the dielectric layer inside the storage node hole, the upper electrode covering the dielectric layer.

摘要翻译： 半导体存储器件的制造方法包括在半导体衬底上形成含碳层，在含碳层上形成绝缘层图案，将含碳层的上表面部分地露出的绝缘层图案， 蚀刻含碳层的暴露部分，形成用于限定存储节点孔的含碳层图案，在存储节点孔内部形成底部电极，在存储节点孔内部的底部电极上形成电介质层， 所述介电层覆盖所述底部电极，并且在所述存储节点孔内部的所述电介质层上形成上部电极，所述上部电极覆盖所述电介质层。

公开(公告)号：US07303957B2

公开(公告)日：2007-12-04

申请号：US11517254

申请日：2006-09-08

申请人： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

发明人： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trenches, and filling the trenches with a first insulating layer, wherein sidewalls of the mask patterns remain exposed after filling the trenches with the first insulating layer. The method further comprises forming spacers on the exposed sidewalls of the mask patterns, filling upper insulating spaces with a second insulating layer thereby defining isolation layers, and removing the mask patterns and the spacers.

公开(公告)号：US20070059876A1

公开(公告)日：2007-03-15

申请号：US11517254

申请日：2006-09-08

申请人： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

发明人： Kyeong-koo Chi ,  Seung-pil Chung ,  Chang-jin Kang ,  Jai-hyuk Song

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： A method of fabricating a flash memory device using a process for forming a self-aligned floating gate is provided. The method comprises forming mask patterns on a substrate, etching the substrate using the mask patterns as an etch mask to form a plurality of trenches, and filling the trenches with a first insulating layer, wherein sidewalls of the mask patterns remain exposed after filling the trenches with the first insulating layer. The method further comprises forming spacers on the exposed sidewalls of the mask patterns, filling upper insulating spaces with a second insulating layer thereby defining isolation layers, and removing the mask patterns and the spacers.

摘要翻译： 提供了一种使用用于形成自对准浮动栅极的工艺来制造闪速存储器件的方法。 该方法包括在衬底上形成掩模图案，使用掩模图案蚀刻衬底作为蚀刻掩模以形成多个沟槽，并用第一绝缘层填充沟槽，其中掩模图案的侧壁在填充沟槽之后保持暴露 与第一绝缘层。 该方法还包括在掩模图案的暴露的侧壁上形成间隔物，用第二绝缘层填充上绝缘空间，从而限定隔离层，以及去除掩模图案和间隔物。