发明授权
US07056832B2 Deep trench self-alignment process for an active area of a partial vertical cell
有权
用于部分垂直单元的活动区域的深沟槽自对准过程
- 专利标题： Deep trench self-alignment process for an active area of a partial vertical cell
- 专利标题（中）： 用于部分垂直单元的活动区域的深沟槽自对准过程
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申请号： US10622965申请日： 2003-07-18
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公开(公告)号： US07056832B2公开(公告)日： 2006-06-06
- 发明人: Ming-Cheng Chang , Yi-Nan Chen , Tse-Yao Huang
- 申请人： Ming-Cheng Chang , Yi-Nan Chen , Tse-Yao Huang
- 申请人地址： TW Taoyuan
- 专利权人： Nanya Technology Corporation
- 当前专利权人： Nanya Technology Corporation
- 当前专利权人地址： TW Taoyuan
- 代理机构： Quintero Law Office
- 优先权： TW92112102A 20030502
- 主分类号： H01L21/302
- IPC分类号： H01L21/302
摘要：
A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.