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    Deep trench self-alignment process for an active area of a partial vertical cell
    1.
    发明授权
    Deep trench self-alignment process for an active area of a partial vertical cell 有权
    用于部分垂直单元的活动区域的深沟槽自对准过程

    公开(公告)号：US07056832B2

    公开(公告)日：2006-06-06

    申请号：US10622965

    申请日：2003-07-18

    申请人： Ming-Cheng Chang ,  Yi-Nan Chen ,  Tse-Yao Huang

    发明人： Ming-Cheng Chang ,  Yi-Nan Chen ,  Tse-Yao Huang

    IPC分类号： H01L21/302

    CPC分类号： H01L27/10864 ,  H01L27/10867

    摘要： A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.

    摘要翻译： 用于部分垂直单元的活动区域的深沟槽自对准过程。 提供具有两个深沟槽的半导体衬底。 在每个深沟槽中形成深沟槽电容器，并在其上形成隔离层。 每个沟槽填充有掩模层。 在深沟槽之间的半导体衬底上形成光致抗蚀剂层，并且光致抗蚀剂层部分地覆盖掩模层。 使用光致抗蚀剂层和掩模层作为掩模，将半导体衬底蚀刻成比隔离层低。 去除光致抗蚀剂层和掩模层，使得深沟槽之间的柱状半导体衬底用作有效区域。

    Trench-capacitor DRAM cell having a folded gate conductor
    2.
    发明授权
    Trench-capacitor DRAM cell having a folded gate conductor 有权
    具有折叠栅极导体的沟槽电容器DRAM单元

    公开(公告)号：US06909136B2

    公开(公告)日：2005-06-21

    申请号：US10604344

    申请日：2003-07-14

    申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

    发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Change-Rong Wu ,  Hui-Min Mao

    IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

    摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

    摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

    TRENCH-CAPACITOR DRAM CELL HAVING A FOLDED GATE CONDUCTOR
    3.
    发明申请
    TRENCH-CAPACITOR DRAM CELL HAVING A FOLDED GATE CONDUCTOR 有权
    具有折叠门控导体的TRENCH-CAPACITOR DRAM单元

    公开(公告)号：US20050012131A1

    公开(公告)日：2005-01-20

    申请号：US10604344

    申请日：2003-07-14

    申请人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

    发明人： Yinan Chen ,  Ming-Cheng Chang ,  Jeng-Ping Lin ,  Tse-Yao Huang ,  Chang-Rong Wu ,  Hui-Min Mao

    IPC分类号： H01L21/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10864 ,  H01L27/10832 ,  H01L29/66181 ,  H01L29/945

    摘要： A novel trench-capacitor DRAM cell structure is disclosed. The trench-capacitor DRAM cell of this invention includes an active area island having a horizontal semiconductor surface and a vertical sidewall contiguous with the horizontal semiconductor surface. A pass transistor is disposed at the corner of the active area island. The pass transistor includes a folded gate conductor strip extending from the horizontal semiconductor surface to the vertical sidewall of the active area island, a source formed in the horizontal semiconductor surface, a drain formed in the vertical sidewall, and a gate oxide layer underneath the folded gate conductor strip. The source and drain define a folded channel. The trench-capacitor DRAM cell further includes a trench capacitor that is insulated from the folded gate conductor strip by a trench top oxide (TTO) layer and is coupled to the pass transistor via the drain.

    摘要翻译： 公开了一种新颖的沟槽电容器DRAM单元结构。 本发明的沟槽电容器DRAM单元包括具有水平半导体表面的有源区域岛和与水平半导体表面邻接的垂直侧壁。 传输晶体管设置在有源区域岛的拐角处。 传输晶体管包括从水平半导体表面延伸到有源区岛的垂直侧壁的折叠栅极导体条，形成在水平半导体表面中的源，在垂直侧壁中形成的漏极和在折叠的下面的栅极氧化物层 栅极导体条。 源极和漏极限定折叠通道。 沟槽电容器DRAM单元还包括沟槽电容器，其通过沟槽顶部氧化层（TTO）层与折叠的栅极导体条绝缘，并且经由漏极耦合到传输晶体管。

    Partial vertical memory cell and method of fabricating the same
    4.
    发明授权
    Partial vertical memory cell and method of fabricating the same 有权
    部分垂直记忆单元及其制造方法

    公开(公告)号：US07033886B2

    公开(公告)日：2006-04-25

    申请号：US10998219

    申请日：2004-11-26

    申请人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

    发明人： Ming-Cheng Chang ,  Yi-Chen Chen ,  Yi-Nan Chen

    IPC分类号： H01L21/8242

    CPC分类号： H01L21/26586 ,  H01L27/10832 ,  H01L27/10838 ,  H01L27/10864 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/1037 ,  H01L29/78 ,  H01L29/945

    摘要： A partial vertical memory cell and fabrication method thereof. A semiconductor substrate is provided, in which two deep trenches having deep trench capacitors respectively are formed, and the deep trench capacitors are lower than a top surface of the semiconductor substrate. A portion of the semiconductor outside the deep trenches is removed to form a pillar between. The pillar is ion implanted to form an ion-doped area in the pillar corner acting as a S/D area. A gate dielectric layer and a conducting layer are conformally formed on the pillar sequentially. An isolation is formed in the semiconductor substrate beside the conducting layer. The conducting layer is defined to form a first gate and a second gate.

    摘要翻译： 局部垂直存储单元及其制造方法。 提供一种半导体衬底，其中分别形成具有深沟槽电容器的两个深沟槽，并且深沟槽电容器低于半导体衬底的顶表面。 在深沟槽外部的半导体的一部分被去除以在其之间形成柱。 柱被离子注入以在柱角中形成作为S / D区域的离子掺杂区域。 栅极电介质层和导电层依次形成在柱上。 在导电层旁边的半导体衬底中形成隔离。 导电层被限定为形成第一栅极和第二栅极。

    Memory device with vertical transistors and deep trench capacitors and method of fabricating the same
    5.
    发明申请
    Memory device with vertical transistors and deep trench capacitors and method of fabricating the same 有权
    具有垂直晶体管和深沟槽电容器的存储器件及其制造方法

    公开(公告)号：US20050167719A1

    公开(公告)日：2005-08-04

    申请号：US11068173

    申请日：2005-02-28

    申请人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

    发明人： Yi-Nan Chen ,  Hui-Min Mao ,  Chih-Yuan Hsiao ,  Ming-Cheng Chang

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L27/10864 ,  H01L27/10867

    摘要： A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

    摘要翻译： 具有垂直晶体管和深沟槽电容器的存储器件。 该器件包括含有至少一个深沟槽和沉积在深沟槽的下部的电容器的衬底。 具有第一导电层和第二导电层的导电结构沉积在沟槽电容器上。 环形绝缘体沉积在侧壁上以及衬底和第一导电层之间。 第一导电层被环形绝缘体包围，并且第二导电层沉积在第一导电层和环形绝缘体上。 在深沟槽的侧壁的一侧上沉积第二导电层和深沟槽的衬底之间的扩散阻挡层。 TTO沉积在导电结构上。 控制门被存放在TTO上。