发明授权
US07071100B2 Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
失效
在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
- 专利标题： Method of forming barrier layer with reduced resistivity and improved reliability in copper damascene process
- 专利标题（中）： 在铜镶嵌工艺中形成具有降低电阻率和改善可靠性的阻挡层的方法
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申请号： US10788912申请日： 2004-02-27
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公开(公告)号： US07071100B2公开(公告)日： 2006-07-04
- 发明人: Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
- 申请人： Kei-Wei Chen , Jung-Chih Tsao , Chi-Wen Liu , Jchung-Chang Chen , Shih-Tzung Chang , Shih-Ho Lin , Yu-Ku Lin , Ying-Lang Wang
- 代理机构： Tung & Associates
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763
摘要：
A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.
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