发明授权
- 专利标题: Semiconductor device, its manufacturing method, and ratio communication device
- 专利标题(中): 半导体器件,其制造方法和比率通信装置
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申请号: US10486707申请日: 2002-05-28
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公开(公告)号: US07119004B2公开(公告)日: 2006-10-10
- 发明人: Tsutomu Ida , Yoshihiko Kobayashi , Masakazu Hashizume , Yoshinori Shiokawa , Sakae Kikuchi
- 申请人: Tsutomu Ida , Yoshihiko Kobayashi , Masakazu Hashizume , Yoshinori Shiokawa , Sakae Kikuchi
- 申请人地址: JP Tokyo JP Tokyo
- 专利权人: Renesas Technology Corp.,Renesas Eastern Japan semiconductor, Inc.
- 当前专利权人: Renesas Technology Corp.,Renesas Eastern Japan semiconductor, Inc.
- 当前专利权人地址: JP Tokyo JP Tokyo
- 代理机构: Mattingly ,Stanger ,Malur & Brundidge, P.C.
- 优先权: JP2001-269160 20010905
- 国际申请: PCT/JP02/05154 WO 20020528
- 国际公布: WO03/023843 WO 20030320
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
The variation of the parasitic inductance generated at the output terminal of a transistor in the final stage of a multistage amplifier unit is reduced. One side of the semiconductor chip that includes the final stage transistor is put in contact with the inner wall of a square recess formed in a wiring substrate. The semiconductor chip is positioned and fixed accurately at the bottom of the recess, whereby the drain wire of the transistor is fixed. Then, a chip edge at which the drain electrode is disposed on top of the chip is put in contact with the inner wall of the recess, which is closer to the drain bonding pad. A metallized layer is formed of the same size as that of the chip at the bottom of the recess and a fusion bonding material is supplied on the metallized layer.
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