Invention Grant
US07235424B2 Method and apparatus for enhanced CMP planarization using surrounded dummy design
有权
使用包围的虚拟设计来增强CMP平坦化的方法和装置
- Patent Title: Method and apparatus for enhanced CMP planarization using surrounded dummy design
- Patent Title (中): 使用包围的虚拟设计来增强CMP平坦化的方法和装置
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Application No.: US11181433Application Date: 2005-07-14
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Publication No.: US07235424B2Publication Date: 2007-06-26
- Inventor: Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
- Applicant: Hsien-Wei Chen , Hao-Yi Tsai , Hsueh-Chung Chen , Shin-Puu Jeng , Jian-Hong Lin , Chih-Tao Lin , Shih-Hsun Hsu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.
Public/Granted literature
- US20070015365A1 Method and apparatus for enhanced CMP planarization using surrounded dummy design Public/Granted day:2007-01-18
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