A semiconductor memory device includes: phase-change memory cells whose states change to a set resistance state or a reset resistance state in response to an applied current pulse; a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal and a set control signal, wherein current amounts of the first through n-th stages are sequentially reduced and are all greater than a reference current amount; a reset pulse driving circuit outputting a reset current pulse in response to a second control signal; a pull-down device activating the set pulse driving circuit and the reset pulse driving circuit in response to a third control signal; and a write driver control circuit outputting the first through third control signals in response to write data, a set pulse width control signal, and a reset pulse width control signal.