公开(公告)号：US07262990B2

公开(公告)日：2007-08-28

申请号：US11253626

申请日：2005-10-20

申请人： Beak-hyung Cho ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0038 ,  G11C13/0069

摘要： A semiconductor memory device includes: phase-change memory cells whose states change to a set resistance state or a reset resistance state in response to an applied current pulse; a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal and a set control signal, wherein current amounts of the first through n-th stages are sequentially reduced and are all greater than a reference current amount; a reset pulse driving circuit outputting a reset current pulse in response to a second control signal; a pull-down device activating the set pulse driving circuit and the reset pulse driving circuit in response to a third control signal; and a write driver control circuit outputting the first through third control signals in response to write data, a set pulse width control signal, and a reset pulse width control signal.

摘要翻译： 半导体存储器件包括：响应于所施加的电流脉冲，其状态改变为设定电阻状态或复位电阻状态的相变存储器单元; 设置脉冲驱动电路，响应于第一控制信号和设定控制信号，输出具有第一至第n级的设定电流脉冲，其中第一至第n级的电流量依次减小并且均大于 参考电流量; 复位脉冲驱动电路，响应于第二控制信号输出复位电流脉冲; 响应于第三控制信号激活所述设定脉冲驱动电路和所述复位脉冲驱动电路的下拉装置; 以及响应写入数据，设定的脉冲宽度控制信号和复位脉冲宽度控制信号而输出第一至第三控制信号的写入驱动器控制电路。

公开(公告)号：US20060087876A1

公开(公告)日：2006-04-27

申请号：US11253626

申请日：2005-10-20

申请人： Beak-hyung Cho ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/0038 ,  G11C13/0069

摘要： A semiconductor memory device includes: phase-change memory cells whose states change to a set resistance state or a reset resistance state in response to an applied current pulse; a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal and a set control signal, wherein current amounts of the first through n-th stages are sequentially reduced and are all greater than a reference current amount; a reset pulse driving circuit outputting a reset current pulse in response to a second control signal; a pull-down device activating the set pulse driving circuit and the reset pulse driving circuit in response to a third control signal; and a write driver control circuit outputting the first through third control signals in response to write data, a set pulse width control signal, and a reset pulse width control signal.

摘要翻译： 半导体存储器件包括：响应于所施加的电流脉冲，其状态改变为设定电阻状态或复位电阻状态的相变存储器单元; 设置脉冲驱动电路，响应于第一控制信号和设定控制信号输出具有第一到第n级的设定电流脉冲，其中第一至第n级的电流量顺序地减小并且都大于a 参考电流量; 复位脉冲驱动电路，响应于第二控制信号输出复位电流脉冲; 响应于第三控制信号激活所述设定脉冲驱动电路和所述复位脉冲驱动电路的下拉装置; 以及响应写入数据，设定的脉冲宽度控制信号和复位脉冲宽度控制信号而输出第一至第三控制信号的写入驱动器控制电路。

公开(公告)号：US07436711B2

公开(公告)日：2008-10-14

申请号：US11779476

申请日：2007-07-18

申请人： Beak-Hyung Cho ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Beak-Hyung Cho ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C11/34

CPC分类号： G11C13/0004 ,  G11C13/0038 ,  G11C13/0069

摘要： A semiconductor memory device includes: phase-change memory cells whose states change to a set resistance state or a reset resistance state in response to an applied current pulse; a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal and a set control signal wherein current amounts of the first through n-th stages are sequentially reduced and are all greater than a reference current amount; a reset pulse driving circuit outputting a reset current pulse in response to a second control signal; a pull-down device activating the set pulse driving circuit and the reset pulse driving circuit in response to a third control signal; and a write driver control circuit outputting the first through third control signals in response to write data, a set pulse width control signal, and a reset pulse width control signal.

摘要翻译： 半导体存储器件包括：响应于所施加的电流脉冲，其状态改变为设定电阻状态或复位电阻状态的相变存储器单元; 设置脉冲驱动电路响应于第一控制信号和设定控制信号输出具有第一到第n级的设定电流脉冲，其中第一至第n级的电流量被顺序地减小并且都大于参考 现金额 复位脉冲驱动电路，响应于第二控制信号输出复位电流脉冲; 响应于第三控制信号激活所述设定脉冲驱动电路和所述复位脉冲驱动电路的下拉装置; 以及响应写入数据，设定的脉冲宽度控制信号和复位脉冲宽度控制信号而输出第一至第三控制信号的写入驱动器控制电路。

公开(公告)号：US07515459B2

公开(公告)日：2009-04-07

申请号：US11315129

申请日：2005-12-23

申请人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

发明人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.

摘要翻译： 提供了一种编程包括多个存储单元的存储器阵列的方法。 存储器单元可以包括相变存储元件。 在一个方面，该方法包括将第一至第n电流脉冲连续地应用于要被编程到第一状态（例如，结晶状态）的每个存储器单元，其中第一至第n电流脉冲的电流幅度随着每个 连续脉冲，并且其中第一至第n电流脉冲的脉冲持续时间随着每个连续脉冲而增加。

公开(公告)号：US07843716B2

公开(公告)日：2010-11-30

申请号：US12031085

申请日：2008-02-14

申请人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

发明人： Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh ,  Joon-min Park

IPC分类号： G11C5/02

CPC分类号： G11C7/067 ,  G11C5/025 ,  G11C5/04 ,  G11C7/062 ,  G11C8/10 ,  G11C8/14 ,  G11C11/16 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/063 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile memory device includes a stack-type memory cell array, a selection circuit and a read circuit. The memory cell array includes multiple memory cell layers and a reference cell layer, which are vertically laminated. Each of the memory cell layers includes multiple nonvolatile memory cells for storing data, and the reference cell layer includes multiple reference cells for storing reference data. The selection circuit selects a nonvolatile memory cell from the memory cell layers and at least one reference cell, corresponding to the selected nonvolatile memory cell, from the reference cell layer. The read circuit supplies a read bias to the selected nonvolatile memory cell and the selected reference cell corresponding to the selected nonvolatile memory cell, and reads data from the selected nonvolatile memory cell.

摘要翻译： 非易失性存储器件包括堆叠型存储单元阵列，选择电路和读取电路。 存储单元阵列包括垂直层叠的多个存储单元层和参考单元层。 每个存储单元层包括用于存储数据的多个非易失性存储单元，参考单元层包括用于存储参考数据的多个参考单元。 选择电路从参考单元层从存储单元层和对应于所选择的非易失性存储单元的至少一个参考单元选择非易失性存储单元。 读取电路向所选择的非易失性存储单元和与所选择的非易失性存储单元相对应的所选择的参考单元提供读偏置，并从所选择的非易失性存储单元读取数据。

公开(公告)号：US07436693B2

公开(公告)日：2008-10-14

申请号：US11319372

申请日：2005-12-29

申请人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh

发明人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C2013/0078

摘要： In one aspect, a semiconductor memory device includes a plurality of phase-change memory cells which are programmed according to a write current applied to the phase-change memory cells, a voltage boosting circuit which receives a first voltage and outputs a boosted voltage which is greater than the first voltage, and a write driver which receives the boosted voltage and which generates the write current from the boosted voltage. In another aspect, the write driver generates the write current corresponding to one of a set current pulse and a reset current pulse, and at least one of the set current pulse and the reset current pulse is gradually increased.

摘要翻译： 一方面，半导体存储器件包括根据施加到相变存储单元的写入电流进行编程的多个相变存储器单元，接收第一电压并输出升压电压的升压电路， 大于第一电压的写驱动器，以及接收升压电压并从升压电压产生写电流的写驱动器。 在另一方面，写入驱动器产生与设定电流脉冲和复位电流脉冲中的一个对应的写入电流，并且设定电流脉冲和复位电流脉冲中的至少一个逐渐增加。

公开(公告)号：US20060220071A1

公开(公告)日：2006-10-05

申请号：US11319372

申请日：2005-12-29

申请人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh

发明人： Sang-beom Kang ,  Du-eung Kim ,  Hyung-rok Oh

IPC分类号： H01L29/768

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0038 ,  G11C2013/0078

摘要： In one aspect, a semiconductor memory device includes a plurality of phase-change memory cells which are programmed according to a write current applied to the phase-change memory cells, a voltage boosting circuit which receives a first voltage and outputs a boosted voltage which is greater than the first voltage, and a write driver which receives the boosted voltage and which generates the write current from the boosted voltage. In another aspect, the write driver generates the write current corresponding to one of a set current pulse and a reset current pulse, and at least one of the set current pulse and the reset current pulse is gradually increased.

摘要翻译： 一方面，半导体存储器件包括根据施加到相变存储单元的写入电流进行编程的多个相变存储器单元，接收第一电压并输出升压电压的升压电路， 大于第一电压的写驱动器，以及接收升压电压并从升压电压产生写电流的写驱动器。 在另一方面，写入驱动器产生与设定电流脉冲和复位电流脉冲中的一个对应的写入电流，并且设定电流脉冲和复位电流脉冲中的至少一个逐渐增加。

公开(公告)号：US20130051114A1

公开(公告)日：2013-02-28

申请号：US13562871

申请日：2012-07-31

申请人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C5/14 ,  G11C11/00 ,  G11C11/16 ,  G11C11/22

CPC分类号： G11C13/0033 ,  G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0042 ,  G11C2013/0054

摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

摘要翻译： 包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。 感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号 第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

公开(公告)号：US07924639B2

公开(公告)日：2011-04-12

申请号：US12031115

申请日：2008-02-14

申请人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Joon-min Park ,  Sang-beom Kang ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C13/0007 ,  G11C5/025 ,  G11C29/787 ,  G11C29/808 ,  G11C29/846 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72

摘要： The present invention provides a nonvolatile memory device that uses a resistance material. The nonvolatile memory device includes: a stacked memory cell array having a plurality of memory cell layers stacked in a vertical direction, the stacked memory cell array having at least one memory cell group and at least one redundancy memory cell group; and a repair control circuit coupled to the stacked memory cell array, the repair control circuit configured to repair a defective one of the at least one memory cell group with a selected one of the at least one redundancy memory cell group. The features that enable repair improve the fabrication yield of the nonvolatile memory device.

摘要翻译： 本发明提供一种使用电阻材料的非易失性存储器件。 非易失性存储器件包括：堆叠存储单元阵列，具有沿垂直方向堆叠的多个存储单元层，所述堆叠存储单元阵列具有至少一个存储单元组和至少一个冗余存储单元组; 以及修复控制电路，其耦合到所述堆叠的存储单元阵列，所述修复控制电路被配置为用所述至少一个冗余存储器单元组中的所选择的一个来修复所述至少一个存储单元组中的有缺陷的一个。 能够修复的特征提高了非易失性存储器件的制造成品率。

公开(公告)号：US08136017B2

公开(公告)日：2012-03-13

申请号：US12036414

申请日：2008-02-25

申请人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho ,  Joon-min Park

发明人： Hyung-rok Oh ,  Sang-beom Kang ,  Woo-yeong Cho ,  Joon-min Park

IPC分类号： G11C29/00

CPC分类号： G06F11/1008 ,  G11C5/02

摘要： Embodiments of the invention provide a multi-layer semiconductor memory device and a related error checking and correction (ECC) method. The multi-layer semiconductor memory device includes first and second memory cell array layers, wherein the first memory cell array layer stores first payload data. The multi-layer semiconductor memory device also includes an ECC engine selectively connected to the second memory cell array layer and configured to receive the first payload data, generate first parity data corresponding to the first payload data, and store the first parity data exclusively in the second memory cell array layer.

摘要翻译： 本发明的实施例提供一种多层半导体存储器件和相关的错误校正和校正（ECC）方法。 多层半导体存储器件包括第一和第二存储单元阵列层，其中第一存储单元阵列层存储第一有效载荷数据。 多层半导体存储器件还包括选择性地连接到第二存储单元阵列层并被配置为接收第一有效载荷数据的ECC引擎，生成与第一有效载荷数据相对应的第一奇偶校验数据，并将第一奇偶校验数据专门存储在 第二存储单元阵列层。