发明授权
- 专利标题： MOS-gated transistor with reduced miller capacitance
- 专利标题（中）： 具有降低的铣刀电容的MOS门控晶体管
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申请号： US10962367申请日： 2004-10-08
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公开(公告)号： US07265415B2公开(公告)日： 2007-09-04
- 发明人: Praveen Muraleedharan Shenoy , Christopher Boguslaw Kocon
- 申请人： Praveen Muraleedharan Shenoy , Christopher Boguslaw Kocon
- 申请人地址： US ME South Portland
- 专利权人： Fairchild Semiconductor Corporation
- 当前专利权人： Fairchild Semiconductor Corporation
- 当前专利权人地址： US ME South Portland
- 代理机构： Townsend and Townsend and Crew LLP
- 主分类号： H01L29/76
- IPC分类号： H01L29/76
摘要：
In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.
公开/授权文献
- US20060076617A1 MOS-gated transistor with reduced miller capacitance 公开/授权日：2006-04-13
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