公开(公告)号：US07534683B2

公开(公告)日：2009-05-19

申请号：US11829262

申请日：2007-07-27

申请人： Praveen Muraleedharan Shenoy ,  Christopher Boguslaw Kocon

发明人： Praveen Muraleedharan Shenoy ,  Christopher Boguslaw Kocon

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

摘要： A trench MOS-gated transistor is formed as follows. A first region of a first conductivity type is provided. A well region of a second conductivity type is then formed in an upper portion of the first region. A trench is formed which extends through the well region and terminates within the first region. Dopants of the second conductivity type are implanted along predefined portions of the bottom of the trench to form regions along the bottom of the trench which are contiguous with the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

摘要翻译： 沟槽MOS门控晶体管如下形成。 提供第一导电类型的第一区域。 然后在第一区域的上部形成第二导电类型的阱区域。 形成了延伸穿过阱区并终止于第一区域内的沟槽。 沿着沟槽底部的预定部分注入第二导电类型的掺杂剂，以沿沟槽底部形成与阱区连续的区域，使得当晶体管处于导通状态时，阱区的较深部分 防止电流流过位于阱区域较深部分正上方的那些沟道区域部分。

公开(公告)号：US20080211012A1

公开(公告)日：2008-09-04

申请号：US12114575

申请日：2008-05-02

申请人： Christopher Boguslaw Kocon ,  Praveen Muraleedharan Shenoy

发明人： Christopher Boguslaw Kocon ,  Praveen Muraleedharan Shenoy

IPC分类号： H01L49/00 ,  H01L21/335

CPC分类号： H01L29/7804 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/6835 ,  H01L21/823487 ,  H01L23/4952 ,  H01L23/49816 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/402 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7815 ,  H01L29/7828 ,  H01L29/7831 ,  H01L29/7838 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2224/16 ,  H01L2924/01012 ,  H01L2924/01078 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H02M3/00 ,  H02M3/33592 ,  H02M7/48 ,  Y02B70/1475 ,  H01L2924/00

摘要： An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions.

摘要翻译： 累积模式场效应晶体管包括第一导电类型的漂移区域，第一导电类型的沟道区域，并且与漂移区域接触并且与漂移区域接触，栅极沟槽具有邻接沟道区域的侧壁。 栅极沟槽延伸到漂移区域并终止于漂移区域内。 晶体管还包括第一导电类型的第一多个硅区域，其形成与沿着第一多个硅区域的垂直壁的沟道区域的P-N结。 第一多个硅区域延伸到漂移区域中，并沿着第一多个硅区域的底部与漂移区域形成P-N结。

公开(公告)号：US07265415B2

公开(公告)日：2007-09-04

申请号：US10962367

申请日：2004-10-08

申请人： Praveen Muraleedharan Shenoy ,  Christopher Boguslaw Kocon

发明人： Praveen Muraleedharan Shenoy ,  Christopher Boguslaw Kocon

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

摘要： In one embodiment of the present invention, a trench MOS-gated transistor includes a first region of a first conductivity type forming a pn junction with a well region of a second conductivity type. The well region has a flat bottom portion and a portion extending deeper than the flat bottom portion. A gate trench extends into the well region. Channel regions extend in the well region along outer sidewalls of the gate trench. The gate trench has a first bottom portion which terminates within the first region, and a second bottom portion which terminates within the deeper portion of the well region such that when the transistor is in an on state the deeper portion of the well region prevents a current from flowing through those channel region portions located directly above the deeper portion of the well region.

摘要翻译： 在本发明的一个实施例中，沟槽MOS门控晶体管包括形成具有第二导电类型的阱区的pn结的第一导电类型的第一区域。 阱区域具有平坦的底部部分和比平坦的底部部分更深的部分。 栅极沟槽延伸到阱区域中。 通道区域沿着栅极沟槽的外侧壁在阱区域中延伸。 栅极沟槽具有终止于第一区域内的第一底部部分和终止于阱区域较深部分内的第二底部部分，使得当晶体管处于导通状态时，阱区域的较深部分防止电流 从而流过位于井区域较深部分正上方的那些通道区域部分。

公开(公告)号：US08772868B2

公开(公告)日：2014-07-08

申请号：US13095670

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Hamza Yilmaz ,  James Pan ,  Rodney S. Ridley, Sr.

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Hamza Yilmaz ,  James Pan ,  Rodney S. Ridley, Sr.

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/0243 ,  H01L21/02579 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/872

摘要： A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.

摘要翻译： 功率器件包括具有多个交替布置的第一和第二导电类型的柱的半导体衬底。 第二导电类型的多个支柱中的至少一个包括设置在第二沟槽的沟槽侧壁上的第二导电类型的第一沟槽外延层和第二沟槽的沟槽底表面，第二沟槽外延层的第二沟槽外延层 设置在第二导电类型的第一沟槽外延层上的导电类型，以及设置在第二导电类型的第二沟槽外延层上的绝缘材料层。

公开(公告)号：US07586156B2

公开(公告)日：2009-09-08

申请号：US11828283

申请日：2007-07-25

申请人： Joseph A. Yedinak ,  Richard L. Woodin ,  Christopher Lawrence Rexer ,  Praveen Muraleedharan Shenoy ,  Kwanghoon Oh ,  Chongman Yun

发明人： Joseph A. Yedinak ,  Richard L. Woodin ,  Christopher Lawrence Rexer ,  Praveen Muraleedharan Shenoy ,  Kwanghoon Oh ,  Chongman Yun

IPC分类号： H01L27/02

CPC分类号： H01L29/872 ,  H01L27/0248 ,  H01L29/1608 ,  H01L29/8618 ,  H01L29/87

摘要： A wide bandgap device in parallel with a device having a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device.

摘要翻译： 宽带隙器件与具有比宽带隙器件更低的雪崩击穿电压和更高的正向压降的器件并联。

公开(公告)号：US08836028B2

公开(公告)日：2014-09-16

申请号：US13095690

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Dwayne S. Reichl ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Dwayne S. Reichl ,  Harold Heidenreich

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/0878 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： In a general aspect, a power device can include at least one N-type epitaxial layer disposed on a substrate and a plurality of N-pillars and P-pillars that define alternating P-N-pillars in the at least one N-type epitaxial layer. The power device can also include an active region and a termination region, where the termination region surrounds the active region. The alternating P-N-pillars can be disposed in both the active region and the termination region, where the termination region can include a predetermined number of floating P-pillars.

摘要翻译： 在一般方面，功率器件可以包括设置在衬底上的至少一个N型外延层和在所述至少一个N型外延层中限定交替的P-N柱的多个N柱和P柱。 功率器件还可以包括有源区和端接区，其中终端区围绕有源区。 交替的P-N柱可以设置在有源区域和终止区域中，其中终止区域可以包括预定数量的浮动P柱。

公开(公告)号：US20120273916A1

公开(公告)日：2012-11-01

申请号：US13095652

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

发明人： Joseph A. Yedinak ,  Christopher L. Rexer ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy ,  Jaegil Lee ,  Hamza Yilmaz ,  Chongman Yun ,  Dwayne S. Reichl ,  James Pan ,  Rodney S. Ridley, SR. ,  Harold Heidenreich

IPC分类号： H01L29/872

CPC分类号： H01L29/0634 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.

公开(公告)号：US06437419B1

公开(公告)日：2002-08-20

申请号：US09450872

申请日：1999-11-29

申请人： Anup Bhalla ,  Praveen Muraleedharan Shenoy

发明人： Anup Bhalla ,  Praveen Muraleedharan Shenoy

IPC分类号： H01L27082

CPC分类号： H01L29/66719 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/66333 ,  H01L29/66371 ,  H01L29/66712 ,  H01L29/7803

摘要： A power semiconductor device has an integral source/emitter ballast resistor. The gate has partial gate structures spaced apart from each other. Emitter resistors are provided beneath sidewall spacers on the ends of the gate structures. The emitter resistors have little effect on the threshold voltage under normal operating conditions, but rapidly saturate the device during short circuit conditions. This in turn increases the short circuit withstand capability o the device.

摘要翻译： 功率半导体器件具有集成的源极/发射极镇流电阻器。 栅极具有彼此间隔开的部分栅极结构。 发射极电阻器设置在栅极结构端部的侧壁间隔物之下。 发射极电阻对正常工作条件下的阈值电压几乎没有影响，但在短路条件下会迅速使器件饱和。 这又增加了器件的短路耐受能力。

公开(公告)号：US08928077B2

公开(公告)日：2015-01-06

申请号：US12234549

申请日：2008-09-19

申请人： JaeGil Lee ,  Chongman Yun ,  Hocheol Jang ,  Christopher L. Rexer ,  Praveen Muraleedharan Shenoy ,  Dwayne S. Reichl ,  Joseph A. Yedinak

发明人： JaeGil Lee ,  Chongman Yun ,  Hocheol Jang ,  Christopher L. Rexer ,  Praveen Muraleedharan Shenoy ,  Dwayne S. Reichl ,  Joseph A. Yedinak

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

CPC分类号： H01L29/66712 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L29/0615 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1075 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one general aspect, a power device includes an active region having a plurality of pillars of a first conductivity type alternately arranged with a plurality of pillars of a second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width. The power device includes a termination region surrounding at least a portion of the active region and having a plurality of pillars of the first conductivity type alternately arranged with a plurality of pillars of the second conductivity type where the plurality of pillars of the second conductivity type in the active region each have substantially the same width and are smaller than each width of the pillars of the second conductivity type in the termination region. The power device includes a transition region disposed between the active region and the termination region.

摘要翻译： 在一个一般方面，功率器件包括具有多个第一导电类型的柱的有源区，该多个柱交替地布置有多个第二导电类型的柱，其中有源区中的第二导电类型的多个柱各自具有 基本相同的宽度。 功率器件包括围绕有源区域的至少一部分的端接区域，并且具有多个第一导电类型的柱，其交替地布置有多个第二导电类型的支柱，其中第二导电类型的多个支柱 有源区域各自具有基本上相同的宽度，并且小于端接区域中的第二导电类型的柱的每个宽度。 功率器件包括设置在有源区和端接区之间的过渡区。

公开(公告)号：US20120276701A1

公开(公告)日：2012-11-01

申请号：US13095678

申请日：2011-04-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Praveen Muraleedharan Shenoy

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42372 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/872

摘要： A power device includes a semiconductor region which in turn includes a plurality of alternately arranged pillars of first and second conductivity type. Each of the plurality of pillars of second conductivity type further includes a plurality of implant regions of the second conductivity type arranged on top of one another along the depth of pillars of second conductivity type, and a trench portion filled with semiconductor material of the second conductivity type directly above the plurality of implant regions of second conductivity type.