发明授权
US07265703B2 Pipelined analog-to-digital converter having interleaved sample-and-hold circuits coupled in common
有权
具有共同耦合的交错采样和保持电路的流水线模数转换器
- 专利标题： Pipelined analog-to-digital converter having interleaved sample-and-hold circuits coupled in common
- 专利标题（中）： 具有共同耦合的交错采样和保持电路的流水线模数转换器
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申请号： US11197586申请日： 2005-08-05
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公开(公告)号： US07265703B2公开(公告)日： 2007-09-04
- 发明人: Fumiyasu Sasaki , Eiki Imaizumi , Takanobu Anbo
- 申请人： Fumiyasu Sasaki , Eiki Imaizumi , Takanobu Anbo
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Mattingly, Stanger, Malur & Brundidge
- 优先权： JP2004-255299 20040902
- 主分类号： H03M1/38
- IPC分类号： H03M1/38
摘要：
A semiconductor integrated circuit device provided with a pipeline A-D conversion circuit in which the enhancement of accuracy and the reduction of power consumption are accomplished is provided. The pipeline A-D conversion circuit is connected in series with an input terminal to which an analog signal to be converted is inputted and has a plurality of stages. The stages other than the first stage connected with the input terminal through at least one stage, including the first stage that receives input signals from the input terminal are constructed as follows: each of the other stages is comprised of two or more sample and hold circuits and an amplifier connected in common with the two or more sample and hold circuits. The two or more sample and hold circuits are caused to perform interleave operation.
公开/授权文献
- US20060044172A1 Semiconductor integrated circuit device 公开/授权日：2006-03-02
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