- 专利标题： Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device
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申请号： US11033322申请日： 2005-01-12
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公开(公告)号： US07268056B2公开(公告)日： 2007-09-11
- 发明人: Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
- 申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： McDermott Will & Emery LLP
- 优先权： JP2001-245209 20010813
- 主分类号： H01L21/76
- IPC分类号： H01L21/76
摘要：
The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
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