公开(公告)号：US07326627B2

公开(公告)日：2008-02-05

申请号：US11822467

申请日：2007-07-06

申请人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

发明人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

IPC分类号： H01L21/76

CPC分类号： H01L27/10873 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上提供氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除氧化膜以暴露上沟槽的底部的至少一部分，并允许氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

公开(公告)号：US07808031B2

公开(公告)日：2010-10-05

申请号：US11822470

申请日：2007-07-06

申请人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

发明人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

IPC分类号： H01L29/423

CPC分类号： H01L27/10873 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

公开(公告)号：US07268056B2

公开(公告)日：2007-09-11

申请号：US11033322

申请日：2005-01-12

申请人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

发明人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

IPC分类号： H01L21/76

CPC分类号： H01L27/10873 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

公开(公告)号：US20050124107A1

公开(公告)日：2005-06-09

申请号：US11033322

申请日：2005-01-12

申请人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

发明人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

IPC分类号： H01L21/8247 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8238 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L27/10873 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

公开(公告)号：US20070269949A1

公开(公告)日：2007-11-22

申请号：US11822467

申请日：2007-07-06

申请人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

发明人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

IPC分类号： H01L21/336

CPC分类号： H01L27/10873 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

公开(公告)号：US20080017903A1

公开(公告)日：2008-01-24

申请号：US11822470

申请日：2007-07-06

申请人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

发明人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

IPC分类号： H01L31/119

CPC分类号： H01L27/10873 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

公开(公告)号：US06849919B2

公开(公告)日：2005-02-01

申请号：US10136404

申请日：2002-05-02

申请人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

发明人： Jun Sumino ,  Satoshi Shimizu ,  Tsuyoshi Sugihara

IPC分类号： H01L21/8247 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00

CPC分类号： H01L27/10873 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/10894

摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.

摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。

公开(公告)号：US20050139908A1

公开(公告)日：2005-06-30

申请号：US11045101

申请日：2005-01-31

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L21/76232 ,  H01L21/76235 ,  H01L27/115

摘要： A semiconductor device includes: a silicon substrate, having a main surface, in which trenches are formed; element isolation oxide films filling in trenches; a tunnel oxide film, formed on main surface located between element isolation oxide film and element isolation oxide film, having birds beak portions in birds beak forms that bring into contact with element isolation oxide film and element isolation oxide film, respectively; and a polysilicon film, formed on tunnel oxide film, having a thickness exceeding 0 and being less than 50 nm in an intermediate portion between element isolation oxide film and element isolation oxide film, and being thinner than the above thickness on birds beak portions. Thereby, it is possible to provide a semiconductor device wherein birds beaks are formed in the gate insulating film so as to have the desired dimensions and wherein the gate insulating film has excellent electrical characteristics.

摘要翻译： 半导体器件包括：具有主表面的硅衬底，其中形成沟槽; 填充在沟槽中的元件隔离氧化膜; 形成在元件隔离氧化膜和元件隔离氧化膜之间的主表面上的隧道氧化膜，分别具有与元件隔离氧化膜和元件隔离氧化膜接触的鸟喙部分的鸟嘴部分; 以及在元件隔离氧化膜和元件隔离氧化膜之间的中间部分中，在隧道氧化膜上形成的厚度超过0且小于50nm的多晶硅膜，并且在鸟嘴部分上比上述厚度薄。 由此，可以提供一种半导体器件，其中在栅极绝缘膜中形成鸟喙以具有期望的尺寸，并且其中栅极绝缘膜具有优异的电气特性。

公开(公告)号：US06906378B2

公开(公告)日：2005-06-14

申请号：US10612913

申请日：2003-07-07

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11536

摘要： There is provided a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having two trenches, an isolation oxide film provided in the trench, a floating gate electrode, an ONO film, and a control gate electrode. The isolation oxide film has an upper surface with a region having a curvature protruding downward. The floating gate electrode has a flat upper surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation oxide films. The ONO film extends from the upper surface of the floating gate electrode to a side surface of the floating gate electrode. The control gate electrode is provided on the ONO film to extend from the upper surface of the floating gate electrode to the side surface of the floating gate electrode.

公开(公告)号：US20050221559A1

公开(公告)日：2005-10-06

申请号：US11131377

申请日：2005-05-18

申请人： Jun Sumino ,  Satoshi Shimizu

发明人： Jun Sumino ,  Satoshi Shimizu

IPC分类号： H01L21/76 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11536

摘要： There is provided a non-volatile semiconductor memory device exhibiting excellent electrical characteristics and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having two trenches, an isolation oxide film provided in the trench, a floating gate electrode, an ONO film, and a control gate electrode. The isolation oxide film has an upper surface with a region having a curvature protruding downward. The floating gate electrode has a flat upper surface and extends from a main surface of the semiconductor substrate between the two trenches to the two isolation oxide films. The ONO film extends from the upper surface of the floating gate electrode to a side surface of the floating gate electrode. The control gate electrode is provided on the ONO film to extend from the upper surface of the floating gate electrode to the side surface of the floating gate electrode.

摘要翻译： 提供了表现出优异的电气特性的非易失性半导体存储器件及其制造方法。 半导体器件包括具有两个沟槽的半导体衬底，设置在沟槽中的隔离氧化膜，浮置栅电极，ONO膜和控制栅电极。 隔离氧化膜具有上表面，具有向下突出的曲率的区域。 浮栅电极具有平坦的上表面，并且从两个沟槽之间的半导体衬底的主表面延伸到两个隔离氧化膜。 ONO膜从浮栅电极的上表面延伸到浮栅电极的侧表面。 控制栅电极设置在ONO膜上，从浮栅电极的上表面延伸到浮栅电极的侧表面。