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1.发明授权Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device 有权制造具有沟槽隔离结构和所得半导体器件的半导体器件的方法公开(公告)号：US07326627B2
公开(公告)日：2008-02-05
申请号：US11822467
申请日：2007-07-06
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L21/76
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上提供氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除氧化膜以暴露上沟槽的底部的至少一部分，并允许氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。
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2.发明申请METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH A TRENCH ISOLATION STRUCTURE AND RESULTING SEMICONDUCTOR DEVICE 失效制造具有耐热隔离结构和半导体器件的半导体器件的方法公开(公告)号：US20080017903A1
公开(公告)日：2008-01-24
申请号：US11822470
申请日：2007-07-06
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L31/119
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。
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3.发明授权Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device 失效制造具有沟槽隔离结构和所得半导体器件的半导体器件的方法公开(公告)号：US06849919B2
公开(公告)日：2005-02-01
申请号：US10136404
申请日：2002-05-02
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/00
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。
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4.发明授权Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device 失效制造具有沟槽隔离结构和所得半导体器件的半导体器件的方法公开(公告)号：US07808031B2
公开(公告)日：2010-10-05
申请号：US11822470
申请日：2007-07-06
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L29/423
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。
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5.发明申请Method of fabricating a semiconductor device with a trench isolation structure and resulting semiconductor device 有权制造具有沟槽隔离结构和所得半导体器件的半导体器件的方法公开(公告)号：US20070269949A1
公开(公告)日：2007-11-22
申请号：US11822467
申请日：2007-07-06
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。
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公开(公告)号：US07268056B2
公开(公告)日：2007-09-11
申请号：US11033322
申请日：2005-01-12
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L21/76
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
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7.发明申请Method of fabricating a semiconductor device with a trench isolation structure and semiconductor device 失效制造具有沟槽隔离结构和半导体器件的半导体器件的方法公开(公告)号：US20050124107A1
公开(公告)日：2005-06-09
申请号：US11033322
申请日：2005-01-12
申请人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
发明人： Jun Sumino , Satoshi Shimizu , Tsuyoshi Sugihara
IPC分类号： H01L21/8247 , H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10873 , H01L21/76229 , H01L21/76232 , H01L21/76235 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： The present fabrication method includes the steps of: providing a nitride film in a main surface of a semiconductor substrate; providing an upper trench, with the nitride film used as a mask; filling the upper trench with an oxide film introduced therein; removing the oxide film to expose at least a portion of a bottom of the upper trench and allowing a remainder of the oxide film to serve as a sidewall; providing a lower trench in a bottom of the upper trench, with the sidewall used as a mask; and with the upper trench having the sidewall remaining therein, providing an oxide film in the upper trench and the lower trench. This can provide a semiconductor device fabrication method and a semiconductor device preventing a contact from penetrating the device in an interconnection process.
摘要翻译： 本发明的制造方法包括以下步骤：在半导体衬底的主表面上设置氮化物膜; 提供上部沟槽，其中所述氮化物膜用作掩模; 用引入其中的氧化膜填充上沟槽; 去除所述氧化物膜以暴露所述上部沟槽的底部的至少一部分并且允许所述氧化膜的其余部分用作侧壁; 在所述上沟槽的底部提供下沟槽，所述侧壁用作掩模; 并且具有保留其侧壁的上沟槽，在上沟槽和下沟槽中提供氧化膜。 这可以提供半导体器件制造方法和半导体器件，以防止接触在互连过程中穿透器件。
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8.发明授权Semi-conductor device with test element group for evaluation of interlayer dielectric and process for producing the same 有权具有用于评估层间电介质的测试元件组的半导体器件及其制造方法公开(公告)号：US06414334B2
公开(公告)日：2002-07-02
申请号：US09852645
申请日：2001-05-11
申请人： Tsuyoshi Sugihara , Satoshi Shimizu
发明人： Tsuyoshi Sugihara , Satoshi Shimizu
IPC分类号： H01L2940
CPC分类号： H01L22/34
摘要： A semiconductor device 10 with Test Element Group (TEG) for estimating an interlayer dielectric includes a memory cell array. The memory cell array includes a semiconductor substrate 1, and a floating gate 2, an interlayer dielectric 3, and a control gate 4, all formed on the substrate 1 in this order. The TEG has the memory cell array similar to semiconductor device subject to estimation for the interlayer dielectric 3. The floating gate 2 has an electrode 5 for estimating the interlayer dielectric 3 provided on at least one side against an elongated direction of the memory cell array.
摘要翻译： 具有用于估计层间电介质的测试元件组（TEG）的半导体器件10包括存储单元阵列。 存储单元阵列包括依次形成在基板1上的半导体基板1，浮置栅极2，层间电介质3和控制栅极4。 TEG具有类似于半导体器件的存储单元阵列，可以估计层间电介质3.浮置栅极2具有用于估计设置在至少一侧的层间电介质3的电极5，用于抵抗存储单元阵列的细长方向。
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公开(公告)号：US06730973B2
公开(公告)日：2004-05-04
申请号：US10319533
申请日：2002-12-16
IPC分类号： H01L2994
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543 , H01L29/511
摘要： A first pattern forming a memory cell is provided on a memory cell region, and a second pattern consisting of a film containing nitrogen atoms is provided on the first pattern. A third pattern forming a gate electrode of a transistor so that the height between the main surface of a semiconductor substrate and the surface of the third pattern is lower than the first pattern is provided on a peripheral circuit region, and a fourth pattern consisting of a film containing nitrogen atoms having a larger thickness than the second pattern is provided on the third pattern in correspondence to the third pattern. The thickness of a portion of the interlayer dielectric film located between the second pattern and a second conductive layer is smaller than the thickness of a portion of the interlayer dielectric film located between the fourth pattern and the second conductive layer.
摘要翻译： 形成存储单元的第一图案设置在存储单元区域上，并且在第一图案上设置由包含氮原子的膜构成的第二图案。 第三图案形成晶体管的栅电极，使得半导体衬底的主表面与第三图案的表面之间的高度低于第一图案，设置在外围电路区域上，第四图案由 对应于第三图案，在第三图案上设置含有比第二图案厚的氮原子的膜。 位于第二图案和第二导电层之间的层间绝缘膜的一部分的厚度小于位于第四图案和第二导电层之间的层间电介质膜的一部分的厚度。
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10.发明授权公开(公告)号：US06417540B1
公开(公告)日：2002-07-09
申请号：US09630018
申请日：2000-07-31
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： The present invention relates to a non-volatile semiconductor memory device, having the higher margin of the implanted ion passing through a source-to-drain electrode, as well as the excellent covering power of an embedded layer deposited in and above a groove within a field oxide region distributed at both the source-to-drain electrode and a source area. The present invention also provides a method for manufacturing the non-volatile semiconductor memory device.
摘要翻译： 本发明涉及一种非易失性半导体存储器件，其具有通过源极 - 漏极电极的注入离子的较高边缘，以及沉积在其内部的沟槽内和之上的嵌入层的优异覆盖功率 分布在源极 - 漏极电极和源极区域的场氧化物区域。本发明还提供了一种用于制造非易失性半导体存储器件的方法。
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