An integrated semiconductor memory device includes a first memory zone, a second memory zone, first address connections and a second address connection. A second address signal present at the second address connection specifies the access to the first or second memory zone, whereas it is specified via first address signals at the first address connections which memory cell is accessed within the first or second memory zone. In a first memory configuration, all address connections are driven externally with address signals and the access to a memory cell in the first or second memory zone is controlled. In a second memory configuration, only the first address connections are driven externally whereas a signaling bit in a mode register regulates the access to the first or second memory zone. This provides for access to the second memory zone even if there is no possibility of externally driving the second address connection.